3.4.5 Message handling unit

Two Message Handling Units (MHU) allow software to raise interrupts to the cores.

Each MHU is mapped to a Secure and a Non-secure area as follows:

  • MHU0 in Non-secure region at 0x4000_3000 and Secure region at 0x5000_3000.
  • MHU1 in Non-secure region at 0x4000_4000 and Secure region at 0x5000_4000.

The APB PPC can control in which areas the MHUs reside.

If there is only one core in the system, MHU1 does not exist and the two regions are reserved. Any accesses to the regions is RAZ/WI.

Only 32-bit writes are supported. Byte and halfword writesare ignored.

See CPU 0 interrupt registers.

Each MHU has the following register map.

Table 3-24 Summary of MHU registers

Offset Name Access Reset value Description
0x000 CPU0INTR_STAT RO 0x0 CPU 0 Interrupt Status Register.
0x004 CPU0INTR_SET WO 0x0 CPU 0 Interrupt Set Register.
0x008 CPU0INTR_CLR WO 0x0 CPU 0 Interrupt Clear Register.
0x00C Reserved - 0x0 Reserved.
0x010 CPU1INTR_STAT RO 0x0 CPU 1 Interrupt Status Register.
0x014 CPU1INTR_SET WO 0x0 CPU 1 Interrupt Set Register.
0x018 CPU1INTR_CLR WO 0x0 CPU 1 Interrupt Clear Register.
0x01C0xFC8 Reserved - 0x0 Reserved.
0xFD0 PIDR4 RO 0x0000_0004 Peripheral ID 4.
0xFD40xFDC Reserved RO 0x0 Reserved.
0xFE0 PIDR0 RO 0x0000_0056 Peripheral ID 0.
0xFE4 PIDR1 RO 0x0000_00B8 Peripheral ID 1.
0xFE8 PIDR2 RO 0x0000_000B Peripheral ID 2.
0xFEC PIDR3 RO 0x0000_0000 Peripheral ID 3.
0xFF0 CIDR0 RO 0x0000_000D Component ID 0.
0xFF4 CIDR1 RO 0x0000_00F0 Component ID 1.
0xFF8 CIDR2 RO 0x0000_0005 Component ID 2.
0xFFC CIDR3 RO 0x0000_00B1 Component ID 3.

CPU 0 interrupt registers

The CPU 0 Interrupt registers, CPU0INTR_STAT, CPU0INTR_SET and CPU0INTR_CLR, allow software to raise an interrupt, clear an interrupt, and also check the value written that is used to raise the interrupt to CPU 0.

Separate Set and Clear registers allow the individual bit of the interrupt status to be set and cleared. This supports software, where each bit is used to represent an event that can be independently set and cleared.

Table 3-25 CPU0INTR_STAT register

Bits Name Access Width Reset value Description
[31:4] Reserved RO 28 0x000000 Reserved
[3:0] CPU0INTR_STAT RO 4 0x0 CPU 0 Interrupt Status. When any bit is set to 1, the MHU interrupt signal to CPU 0 is set to HIGH.

Table 3-26 CPU0INTR_SET register

Bits Name Access Width Reset value Description
[31:4] Reserved RO 28 0x000000 Reserved
[3:0] CPU0INTR_SET WO 4 0x0 CPU 0 Interrupt Set. When a 1 is written to CPU0INTR_SET[n], the corresponding CPU0INTR_STAT[n] signal is set to HIGH.

Table 3-27 CPU0INTR_CLR register

Bits Name Access Width Reset value Description
[31:4] Reserved RO 28 0x000000 Reserved
[3:0] CPU0INTR_CLR WO 4 0x0 CPU 0 Interrupt Set. When a 1 is written to CPU0INTR_CLR[n], the corresponding CPU0INTR_STAT[n] signal is set to LOW.

CPU 1 interrupt registers

The CPU 1 Interrupt registers, CPU1INTR_STAT, CPU1INTR_SET and CPU1INTR_CLR, allow software to raise an interrupt, clear an interrupt, and also check that the value written is used to raise the interrupt to CPU 1.

Separate Set and Clear registers allow the individual bit of the interrupt status to be set and cleared. This supports software, where each bit is used to represent an event that can be independently set and cleared.

Note:

In a single processor system, these registers do not exist. Any access to the registers results in RAZ/WI.

Table 3-28 CPU1INTR_STAT register

Bits Name Access Width Reset value Description
[31:4] Reserved RO 28 0x000000 Reserved
[3:0] CPU1INTR_STAT RO 4 0x0 CPU 1 Interrupt Status. When any bit is set to 1, the MHU interrupt signal to CPU 1 is set to HIGH.

Table 3-29 CPU1INTR_SET register

Bits Name Access Width Reset value Description
[31:4] Reserved RO 28 0x000000 Reserved
[3:0] CPU1INTR_SET WO 4 0x0 CPU 1 Interrupt Set. When a 1 is written to CPU1INTR_SET[n], the corresponding CPU1INTR_STAT[n] signal is set to HIGH.

Table 3-30 CPU1INTR_CLR register

Bits Name Access Width Reset value Description
[31:4] Reserved RO 28 0x000000 Reserved
[3:0] CPU1INTR_CLR WO 4 0x0 CPU 1 Interrupt Set. When a 1 is written to CPU1INTR_CLR[n], the corresponding CPU1INTR_STAT[n] signal is set to LOW.
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