A.10 Interrupt parameters

Interrupt parameters

The following table lists the top-level Verilog parameters that configure the interrupts.

Table A-26 Parameters that configure the interrupts

Parameter Default value Description
CPU0_EXP_NUMIRQ 64 Sets the number of interrupts on the expansion subsystem that connect to CPU element 0. Minimum value of 2, maximum 448.
CPU1_EXP_NUMIRQ Sets the number of interrupts on the expansion subsystem that connect to CPU element 1. Minimum value of 2, maximum 448.
CPU0_EXP_IRQDIS_DEF[447:0] {{(448-16){1`b0}}, 16`b1010101010101010} Verilog parameter with fixed width, for providing the default value of the related Verilog parameter, which must not be modified. The name of the related Verilog parameter differs with the non-existence of the _DEF suffix. The width of the parameter equals the utmost width of the related parameter, therefore arbitrary range selection can be performed on the assignment of the default value of the related parameter.
CPU0_EXP_IRQDIS [CPU0_EXP_NUMIRQ−1:0] CPU0_EXP_IRQDIS_DEF [CPU0_EXP_NUMIRQ−1:0] When a bit is set to 1, it disables the corresponding expansion interrupt, IRQ[n+32], on CPU element 0.
CPU1_EXP_IRQDIS [CPU1_EXP_NUMIRQ−1:0]

CPU1_EXP_NUMIRQ{1`b0}

When a bit is set to 1, it disables the corresponding expansion interrupt, IRQ[n+32], on CPU element 1.
CPU0_EXP_WAKEUPDIS_DEF[447:0] {{(448-16){1`b0}}, 16`b1111111100000000} Verilog parameter with fixed width for providing the default value of the related Verilog parameter, which must not be modified. The name of the related Verilog parameter differs with the non-existence of the _DEF suffix. The width of the parameter equals the utmost width of the related parameter, therefore arbitrary range selection can be performed on the assignment of the default value of the related parameter.
CPU0_EXP_WAKEUPDIS [CPU0_EXP_NUMIRQ−1:0] CPU0_EXP_WAKEUPDIS_DEF [CPU0_EXP_NUMIRQ−1:0] When a bit is set to 1, it disables the corresponding External Wakeup Controller (EWC) expansion interrupt, IRQ[n+32], on CPU element 0.
CPU1_EXP_WAKEUPDIS [CPU1_EXP_NUMIRQ−1:0] CPU1_EXP_NUMIRQ{1`b0} When a bit is set to 1, it disables the corresponding EWC expansion interrupt, IRQ[n+32], on CPU element 1.
CPU0_EXP_IRQ_SYNC_EN_DEF[447:0] {{(448-16){1`b0}}, 16`b1111000011110000} Verilog parameter with fixed width for providing the default value of the related Verilog parameter, which must not be modified. The name of the related Verilog parameter differs with the non-existence of the _DEF suffix. The width of the parameter equals the utmost width of the related parameter, therefore arbitrary range selection can be performed on the assignment of the default value of the related parameter.
CPU0_EXP_IRQ_SYNC_EN [CPU0_EXP_NUMIRQ−1:0] CPU0_EXP_IRQ_SYNC_EN_DEF [CPU0_EXP_NUMIRQ−1:0] When bit[n] is set to 1, it enables synchronization for the corresponding expansion interrupt, IRQ[n+32], for CPU element 0.
CPU1_EXP_IRQ_SYNC_EN [CPU1_EXP_NUMIRQ−1:0] CPU1_EXP_NUMIRQ{1`b0} When bit[n] is set to 1, it enables synchronization for the corresponding expansion interrupt, IRQ[n+32], for CPU element 1.
CPU0_EXP_NMI_SYNC_EN 0 When set to 1, it enables synchronization for the expansion NMI interrupt of CPU element 0.
CPU1_EXP_NMI_SYNC_EN 0 When set to 1, it enables synchronization for the expansion NMI interrupt of CPU element 1.
CPU0_EXP_NMI_PULSE_SPT_EN 0 When set to 1, it enables pulse capture for the expansion NMI interrupt of CPU element 0.
CPU1_EXP_NMI_PULSE_SPT_EN 0 When set to 1, it enables pulse capture for the expansion NMI interrupt of CPU element 1.
CPU0_EXP_IRQ_PULSE_SPT_EN_DEF[447:0] {{(448-16){1`b0}}, 16`b1100110011001100} Verilog parameter with fixed width for providing the default value of the related Verilog parameter, which must not be modified. The name of the related Verilog parameter differs with the non-existence of the _DEF suffix. The width of the parameter equals the utmost width of the related parameter, therefore arbitrary range selection can be performed on the assignment of the default value of the related parameter.
CPU0_EXP_IRQ_PULSE_SPT_EN [CPU0_EXP_NUMIRQ−1:0] CPU0_EXP_IRQ_PULSE_SPT_EN_DEF [CPU0_EXP_NUMIRQ−1:0] When bit[n] is set to 1, it enables pulse capture for the corresponding expansion interrupt, IRQ[n+32], for CPU element 0.
CPU1_EXP_IRQ_PULSE_SPT_EN [CPU1_EXP_NUMIRQ−1:0] CPU1_EXP_NUMIRQ{1'b0} When bit[n] is set to 1, it enables pulse capture for the corresponding expansion interrupt, IRQ[n+32], for CPU element 1.
CPU0_INT_IRQLATENCY[31:0] 32{1`b0} When bit[n] is set to 1, it uses the lowest latency for the corresponding internal interrupt, IRQ[n], for CPU element 0.
CPU0_EXP_IRQLATENCY [CPU0_EXP_NUMIRQ−1:0] CPU0_EXP_NUMIRQ{1'b0} When bit[n] is set to 1, it uses the lowest latency for the corresponding expansion interrupt, IRQ[n+32], for CPU element 0.
CPU1_INT_IRQLATENCY[31:0] 32{1`b0} When bit[n] is set to 1, it uses the lowest latency for the corresponding internal interrupt, IRQ[n], for CPU element 1.
CPU1_EXP_IRQLATENCY [CPU1_EXP_NUMIRQ−1:0] CPU1_EXP_NUMIRQ{1'b0} When bit[n] is set to 1, it uses the lowest latency for the corresponding expansion interrupt, IRQ[n+32], for CPU element 1.
CPU0_INTNMI_ENABLE_RST 1

Sets the reset value of the CPU0_INTNMI_ENABLE bit in the NMI_ENABLE register.

The CPU0_INTNMI_ENABLE bit controls:

  • 1 = The SSE-200 internal interrupts sources can set the NMI interrupt on CPU element 0.
  • 0 = The SSE-200 internal interrupts sources cannot set the NMI interrupt on CPU element 0.
CPU1_INTNMI_ENABLE_RST 0

Sets the reset value of the CPU1_INTNMI_ENABLE bit in the NMI_ENABLE register.

The CPU1_INTNMI_ENABLE bit controls:

  • 1 = The SSE-200 internal interrupts sources can set the NMI interrupt on CPU element 1.
  • 0 = The SSE-200 internal interrupts sources cannot set the NMI interrupt on CPU element 1.
CPU0_EXPNMI_ENABLE_RST 1

Sets the reset value of the CPU0_EXPNMI_ENABLE bit in the NMI_ENABLE register.

The CPU0_EXPNMI_ENABLE bit controls:

  • 1 = The CPU0EXPNMI signal can set the NMI interrupt on CPU element 0.
  • 0 = The CPU0EXPNMI signal cannot set the NMI interrupt on CPU element 0.
CPU1_EXPNMI_ENABLE_RST 0

Sets the reset value of the CPU1_EXPNMI_ENABLE bit in the NMI_ENABLE register.

The CPU1_EXPNMI_ENABLE bit controls:

  • 1 = The CPU1EXPNMI signal can set the NMI interrupt on CPU element 1.
  • 0 = The CPU1EXPNMI signal cannot set the NMI interrupt on CPU element 1.
CPU0_IRQ_LVL 4 Sets the number of interrupt priority levels, 2CPU0_IRQ_LVL, that the NVIC in CPU element 0 supports.
CPU1_IRQ_LVL 4 Sets the number of interrupt priority levels, 2CPU1_IRQ_LVL, that the NVIC in CPU element 1 supports.
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