3.6.1 System control registers

The System Control Region contains the peripherals in the System Control element.

The System Control Region occupies the following areas:

  • 0x4002_0000 to 0x4003_FFFF, which is Non-secure
  • 0x5002_0000 to 0x5003_FFFF, which is Secure.

Table 3-62 System control regions

Row ID (alias) Address Size Region name Description Security
  From To        
1 (5) 0x4002_0000 0x4002_0FFF 4KB SYSINFO System Information Registers Block. NS
2 0x4002_1000 0x4002_EFFF   Reserved Reserveda  
3 (18) 0x4002_F000 0x4002_FFFF 4KB S32KTIMER CMSDK Timer running on S32KCLK. NS-PPC
4 0x4003_0000 0x4003_FFFF   Reserved Reserved  
5 (1) 0x5002_0000 0x5002_0FFF 4KB SYSINFO System Information Registers Block. S
6 0x5002_1000 0x5002_1FFF 4KB SYSCONTROL System Control Registers Block. SP
7 0x5002_2000 0x5002_2FFF 4KB SYS_PPU System Power Policy Unit. SP
8 0x5002_3000 0x5002_3FFF 4KB CPU0CORE_PPU CPU 0 Core Power Policy Unit. SP
9 0x5002_4000 0x5002_4FFF 4KB CPU0DEBUG_PPUb CPU 0 Debug Power Policy Unit. SP
10 0x5002_5000 0x5002_5FFF 4KB CPU1CORE_PPU CPU 1 Core Power Policy Unit. SP
11 0x5002_6000 0x5002_6FFF 4KB CPU1DEBUG_PPUb CPU 1 Debug Power Policy Unit. SP
12 0x5002_7000 0x5002_7FFF 4KB CRYPTO_PPU CryptoCell Power Policy Unit. SP
- 0x5002_8000 0x5002_8FFF 4KB Reserved Reservedc  
13 0x5002_9000 0x5002_9FFF 4KB DEBUG_PPU System Debug Power Policy Unit. SP
14 0x5002_A000 0x5002_AFFF 4KB RAM0_PPU SRAM Bank 0 Power Policy Unit. SP
15 0x5002_B000 0x5002_BFFF 4KB RAM1_PPU SRAM Bank 1 Power Policy Unit. SP
16 0x5002_C000 0x5002_CFFF 4KB RAM2_PPU SRAM Bank 2 Power Policy Unit. SP
17 0x5002_D000 0x5002_DFFF 4KB RAM3_PPU SRAM Bank 3 Power Policy Unit. SP
18 0x5002_E000 0x5002_EFFF 4KB S32KWATCHDOG CMSDK Watchdog on S32KCLK. SP
19 (3) 0x5002_F000 0x5002_FFFF 4KB S32KTIMER CMSDK Timer on S32KCLK. S-PPC
20 0x5003_0000 0x5003_FFFF   Reserved Reserved.  

Note:

  • For NS_PPC, any Secure access targeting these regions is blocked. PPCs control Non-secure access to these regions.
  • For S_PPC, any Non-Secure access targeting this region is blocked. PPCs control Secure access to this region.
  • NSP indicates Non-secure private access only.
  • SP indicates Secure privilege access only.
  • S indicates Secure access only.
  • 0x4003_0000-0x4003_FFFF and 0x5003_0000-0x5003_FFFF respond with error.
a This region is RAZ/WI.
b CPU0DEBUG_PPU and CPU1DEBUG_PPU regions do not exist if SEPARATE_CPUDEBUG_PD configuration is 0, indicating that separate CPU debug power domains is not supported. If they do not exist, these regions are RAZ/WI.
c This region is RAZ/WI.
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