3.2.5 System control overview

The System Control region contains the peripherals in the System Control element. The System control region occupies two areas:

  • 0x4002_0000-0x4003_FFFF, which is Non-secure.
  • 0x5002_0000-0x5003_FFFF, which is Secure.

The following table shows the System control regions.

Table 3-5 System control regions

Row ID (alias) Address Size Region name Description Security
  From To        
1 (5) 0x4002_0000 0x4002_0FFF 4KB SYSINFO System Information Registers Block. NS
2 0x4002_1000 0x4002_EFFF - - Reserved, RAZ/WI. -
3 (18) 0x4002_F000 0x4002_FFFF 4KB S32KTIMER CMSDK Timer running on S32KCLK. NS-PPC
4 0x4003_0000 0x4003_FFFF - - Reserved. -
5 (1) 0x5002_0000 0x5002_0FFF 4KB SYSINFO System Information Registers Block. S
6 0x5002_1000 0x5002_1FFF 4KB S_SYSCONTROL System Control Registers Block. SP
7 0x5002_2000 0x5002_2FFF 4KB SYS_PPU System Power Policy Unit. SP
8 0x5002_3000 0x5002_3FFF 4KB CPU0CORE_PPU CPU 0 Core Power Policy Unit. SP
9 0x5002_4000 0x5002_4FFF 4KB CPU0DEBUG_PPUa CPU 0 Debug Power Policy Unit. SP
10 0x5002_5000 0x5002_5FFF 4KB CPU1CORE_PPU CPU 1 Core Power Policy Unit. SP
11 0x5002_6000 0x5002_6FFF 4KB CPU1DBG_PPUa CPU 1 Debug Power Policy Unit. SP
  0x5002_7000 0x5002_8FFF 4KB - Reserved, RAZ/WI. -
12 0x5002_9000 0x5002_9FFF 4KB DBG_PPU System Debug Power Policy Unit. SP
13 0x5002_A000 0x5002_AFFF 4KB RAM0_PPU SRAM Bank 0 Power Policy Unit. SP
14 0x5002_B000 0x5002_BFFF 4KB RAM1_PPU SRAM Bank 1 Power Policy Unit. SP
15 0x5002_C000 0x5002_CFFF 4KB RAM2_PPU SRAM Bank 2 Power Policy Unit. SP
16 0x5002_D000 0x5002_DFFF 4KB RAM3_PPU SRAM Bank 3 Power Policy Unit. SP
17 0x5002_E000 0x5002_EFFF 4KB S32KWATCHDOG CMSDK Watchdog on S32KCLK. SP
18 (3) 0x5002_F000 0x5002_FFFF 4KB S32KTIMER CMSDK Timer on S32KCLK. S-PPC
19 0x5003_0000 0x5003_FFFF - - Reserved. -


  • For NS_PPC, any Secure access targeting this region is blocked. A PPC controls Non-secure access to this region.
  • For S_PPC, any Non-secure access targeting this region is blocked. A PPC controls Secure access targeting this region.
  • NSP indicates Non-secure privilege access only.
  • SP indicates Secure privilege access only.
  • S indicates Secure access only.
  • Reserved regions respond with RAZ/WI when accessed. The System Information Registers Block is mapped to both the Secure and Non-secure region and is visible to both without any security protection.
a CPU0DBG_PPU and CPU1DBG_PPU regions do not exist if separate CPU debug power domains are not supported.
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.