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If the CryptoCell-312 exists, then the SSE-200 implements a Persistent State Storage Block that resides in the PD_AON power domain. It implements registers that store key state information on behalf of CryptoCell.
See the Arm® CoreLink™ SSE-200 Subsystem for Embedded Configuration and Integration Manual for more information.
The Crypto element in general is reset by Warm reset.
However, the persistent state storage values are reset to zeros only by Cold reset. If a system Warm reset is triggered, the contents in the persistent state storage are not cleared. CryptoCell, when restarting, then discovers that the persistent state values are populated and does not try to regenerate it from the One Time Programmable (OTP) values. Therefore, if Trusted Firmware decides to lock fields in the persistent state storage, it is not possible to unlock it through Warm reset. This can cause problems at boot.
In addition, since Warm reset conceptually can be triggered at any time, it could interfere with, and cause corruption of data during writing of the persistent state storage.
Warm reset can only be triggered by each processor writing to its AIRCR.SYSRESETREQ control. The hardware requests are then gated by the SYSRSTREQ0_EN and SYSRSTREQ1_EN values in the RESET_MASK register. To avoid problems with persistent state storage, by default, these gating values are set to LOW using the input parameters SYSRSTREQ0_EN_RST and SYSRSTREQ1_EN_RST to disable Warm reset. Secure firmware can allow it at a later stage after checking that it is safe to allow Warm reset, for example, if: