2.9.5 External wakeup controllers

Each Cortex®-M33 core in SSE-200 subsystem is configured to have a Wakeup Interrupt Controller (WIC). These WICs:

  • Allow each Cortex-M33, during DEEPSLEEP, to go into a lower power mode, where the core and the NVIC clocks are turned off and optionally placed into Retention.
  • Store the interrupt masks from the NVIC in the WIC, holding any outstanding interrupts.
  • Raise a request to wake the core if the masks allow it.

This WIC however does not support waking the Cortex-M33 core if power to the core and the NVIC is turned OFF.

To support waking the Cortex-M33 cores from an OFF state, SSE-200 subsystem implements an External Wakeup Controller (EWC) for each processor.

The EWC uses the wakeup mask already stored in the WIC and performs the task of holding any pulse type interrupts on behalf of the WIC and NVIC, when the CPU clocks are OFF. It also wakes the CPU if the masks allow it, as long as for that associated CPU n interrupt pin x, the corresponding parameters are as follows:

  • If the interrupt is NMI then set CPU<n>_EXP_NMI_PULSE_SPT_EN to ‘1’. Else set CPU<n>_EXP_IRQ_PULSE_SPT_EN<x> to ‘1’.
  • If the interrupt is not NMI, set CPU<n>_EXP_WAKEUPDIS<x> to ‘0’.

Before allowing a processor to move to the OFF state, with the intention to use interrupts to wake it later, you must:

  1. Enable its associated WIC using the WICCTRL register.
  2. Use the EWCTRL register to enable its associated EWC.
  3. After the processor re-awakes and has boot to a point to be able to handle interrupts, the associated EWC<N>EN_CLR must be used to clear the EWC.

Note:

  • If a processor is powered down without enabling its associated EWC, interrupts cannot power up the processor. To force a processor in this state to power up, you must either:

    • Write to the PPU and set its power policy register to ON.

    • Use the external debugger to wake the processor with the associated GPR.

    This feature allows you to more permanently leave the secondary core powered off. The feature still allows you to bring the secondary core back into use if necessary, later.

  • The EWC does not deal with the event interface and therefore does not support waking the core from an OFF state using events.
  • If any EWC wakes its associated processor, it also wakes the main system (PD_SYS).
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