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Each Cortex®-M33 core in SSE-200 subsystem is configured to have a Wakeup Interrupt Controller (WIC). These WICs:
This WIC however does not support waking the Cortex-M33 core if power to the core and the NVIC is turned OFF.
To support waking the Cortex-M33 cores from an OFF state, SSE-200 subsystem implements an External Wakeup Controller (EWC) for each processor.
The EWC uses the wakeup mask already stored in the WIC and performs the task of holding any pulse type interrupts on behalf of the WIC and NVIC, when the CPU clocks are OFF. It also wakes the CPU if the masks allow it, as long as for that associated CPU n interrupt pin x, the corresponding parameters are as follows:
Before allowing a processor to move to the OFF state, with the intention to use interrupts to wake it later, you must:
If a processor is powered down without enabling its associated EWC, interrupts cannot power up the processor. To force a processor in this state to power up, you must either:
Write to the PPU and set its power policy register to ON.
This feature allows you to more permanently leave the secondary core powered off. The feature still allows you to bring the secondary core back into use if necessary, later.