2.9.4 System boot when powering up

The power mode of the PPU, along with its integration, ensures that the following domains can power up immediately after Cold reset:

  • PD_CPU0CORE.
  • PD_CPU1CORE.
  • PD_SYS.
  • PD_CRYPTO.
  • PD_SRAM0 to PD_SRAM3.

The automatic powering up of PD_CPU0CORE and PD_CPU1CORE is also dependent on the settings of the CPU0_WAIT and CPU1_WAIT respectively in CPUWAIT register:

  • If a bit in CPUWAIT is set to HIGH, out of Cold reset, the associated processor will not power up.

    This allows you to control which of the processors powerup after Cold reset conditions.

  • The use of the CPUWAIT register to control powering up is in addition to the other functionality of CPUWAIT, which is to delay the boot of each associated processor after powering up or reset.
  • The parameters CPU0WAIT_RST and CPU1WAIT_RST set the reset values of CPU0_WAIT and CPU1_WAIT, respectively.

Warm resets do not depend on CPUWAIT.

After a core has been powered up and powered down, without reapplying a Cold reset that depends on the settings in CPUWAIT, the CPUWAIT register is not involved in delaying the powerup of the cores, but is involved to delay the boot of the corresponding processor.

Note:

If a processor is not expected to power up, a debugger from the GPR registers is still able to make a request for it to power up. To prevent the processor running invalid code, at least one of the following is needed:
  • Ensure that boot vector INITSVTOR0 and INITSVTOR1 are pointing to valid boot code locations, even if it is simply to place the core back to DeepSleep and WFI, and therefore turn off the processor. This ensures that no invalid code is ever executed.
  • Set the associated CPUWAIT bits of the processor that is not expected to run to HIGH, or ensure that it defaults to HIGH at Cold reset. This ensures that the processor does not run code or does not power up without Secure software or Secure debug clearing the associated CPUWAIT bits.
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.