3.6.4 System Control Register block

The System Control Register Block implements registers for power, clocks, resets, and other general system control.

This module resides at base address 0x5002_1000 in the Secure region of the base peripheral region. The System Control Register Block is Secure privilege access only.

For write access to these registers, only 32-bit writes are supported. Any byte or halfword writes are ignored. The following table lists the registers in this block.

Table 3-66 Summary of System Control registers

Offset Name Access Reset Description
0x000 SECDBGSTAT RO 0x0000_0000 Secure Debug Configuration Status.
0x004 SECDBGSET WO 0x0000_0000 Secure Debug Configuration Set.
0x008 SECDBGCLR WO 0x0000_0000 Secure Debug Configuration Clear.
0x00C SCSECCTRL RW 0x0000_0000 System Control Security Control.
0x010 FCLK_DIV RW Parameterized Fast Clock Divider Configuration.
0x014 SYSCLK_DIV RW Parameterized System Clock Divider Configuration.
0x018 CLOCK_FORCE RW 0x0000_06FF Clock Force.
0x01C0x0FC - RO 0x0000_0000 Reserved.
0x100 RESET_SYNDROME RW 0x0000_0001

Reset Syndrome.

Register only cleared at Power-up reset.

0x104 RESET_MASK RW

Partially parameterized (other bits reset to '0' or reserved).

Reset Mask.
0x108 SWRESET WO 0x0000_0000 Software Reset.
0x10C GRETREG RW 0x0000_0000 General Purpose Retention.
0x110 INITSVRTOR0 RW Static tied input Initial Secure Reset Vector Register For CPU 0.
0x114 INITSVRTOR1 RW Static tied input Initial Secure Reset Vector Register For CPU 1.
0x118 CPUWAIT RW Parameterized CPU Boot wait control after reset.
0x11C NMI_ENABLE RW Parameterized NMI Enable Register.
0x120 WICCTRL RW 0x0000_0000 WIC request and acknowledge handshake.
0x124 EWCTRL RW 0x0000_0000 External Wakeup Control.
0x1280x1FF - - 0x0000_0000 Reserved.
0x200 PDCM_PD_SYS_SENSE RW 0x0000_007F Power Control Depedendency Matrix PD_SYS Power Domain Sensitivity.
0x204 - - 0x0000_0000 Reserved.
0x208 - - 0x0000_0000 Reserved.
0x20C PDCM_PD_SRAM0_SENSE RW 0x0000_0000 Power Control Depedendency Matrix PD_SRAM0 Power Domain Sensitivity.
0x210 PDCM_PD_SRAM1_SENSE RW 0x0000_0000 Power Control Depedendency Matrix PD_SRAM1 Power Domain Sensitivity.
0x214 PDCM_PD_SRAM2_SENSE RW 0x0000_0000 Power Control Depedendency Matrix PD_SRAM2 Power Domain Sensitivity.
0x218 PDCM_PD_SRAM3_SENSE RW 0x0000_0000 Power Control Depedendency Matrix PD_SRAM3 Power Domain Sensitivity.
0x21C0x22C - - - Reserved.
0x230 - - 0x0000_0000 Reserved.
0x2340x23C - - 0x0000_0000 Reserved.
0x2400x24C - - 0x0000_0000 Reserved.
0x2500xFCC - - - Reserved.
0xFD0 PIDR4 RO 0x0000_0004 Peripheral ID 4.
0xFD4 PIDR5 RO 0x0000_0000 Reserved.
0xFD8 PIDR6 RO 0x0000_0000 Reserved.
0xFDC PIDR7 RO 0x0000_0000 Reserved.
0xFE0 PIDR0 RO 0x0000_0054 Peripheral ID 0.
0xFE4 PIDR1 RO 0x0000_00B8 Peripheral ID 1.
0xFE8 PIDR2 RO 0x0000_001B Peripheral ID 2.
0xFEC PIDR3 RO 0x0000_0000 Peripheral ID 3.
0xFF0 CIDR0 RO 0x0000_000D Component ID 0.
0xFF4 CIDR1 RO 0x0000_00F0 Component ID 1.
0xFF8 CIDR2 RO 0x0000_0005 Component ID 2.
0xFFC CIDR3 RO 0x0000_00B1 Component ID 3.

SECDBGSTAT, SECDBGSET, and SECDBGCLR

The Secure Debug Configuration registers are used to select the source value for the combined Secure Debug Authentication signals DBGEN, NIDEN, SPIDEN, and SPNIDEN.

For each signal, a selector is provided to select between an internal register value and the value on the boundary of the SSE-200.

Secure software can set each value by setting the associated bit in the SECDBGSET register, or clear a value by setting the associated bit in the SECDBGCLR register.

Secure software can read the system-wide value by reading the associated SECDBGSTAT register bit.

For example, DBGEN_SEL selects the source of the DBGEN value that is used in the system, where:

  • DBGEN_SEL is 0, the input DBGENIN signal is used to define the system-wide DBGEN value.
  • DBGEN_SEL is 1, the internal register value DBGEN_I is used to define the system-wide DBGEN value.

For example:

  • To set DBGEN_I to 1, write to the SECDBGSET register with DBGEN_I_SET set to 1.
  • To set DBGEN_SEL to 1, write to the SECDBGSET register with DBGEN_SEL_SET set to 1.
  • To set DBGEN_I to 0, write to the SECDBGCLR register with DBGEN_I_CLR set to 1.
  • To set DBGEN_SEL to 0, write to the SECDBGCLR register with DBGEN_SEL_CLR set to 1.
  • To read the value of DBGEN, read the SECDBGSTAT register for the DBGEN_SEL_STAT value.

The DGBEN value is also made available to external expansion logic from the DBGEN output signal of the SSE-200.

nPORESETAON resets these registers.

Top-level static configuration signals DBGENSELDIS, NIDENSELDIS, SPIDENSELDIS, and SPNIDENSELDIS are provided to enable each of the selectors, DBGEN_SEL_STATUS, NIDEN_SEL_STATUS, SPIDEN_SEL_STATUS, and SPNIDEN_SEL_STATUS respectively to be forced to zero, forcing each respective input to use its external value. This method can be used to prevent Secure firmware from modifying or overriding the Debug Authentication value, in particular, when the Crypto element is present (when HAS_CRYPTO == 1) in the system and the intention is to use signals that are derived from CRYPTODCUEN[127:1] to control the Debug Authentication signal.

The following table lists the bits for the Secure Debug Configuration Status register.

Table 3-67 SECDBGSTAT register

Bits Name Access Reset value Description
[31:8] Reserved RO 0x0 Reserved
7 SPNIDEN_SEL_STATUS RO 0 Secure privilege non-invasive debug enable selector value.
6 SPNIDEN_STATUS RO SPNIDENINa Secure privilege non-invasive debug enable value.
5 SPIDEN_SEL_STATUS RO 0 Secure privilege invasive debug enable selector value.
4 SPIDEN_I_STATUS RO SPIDENINa Secure privilege invasive debug enable value.
3 NIDEN_SEL_STATUS RO 0 Non-invasive debug enable selector value.
2 NIDEN_I_STATUS RO NIDENINa Non-invasive debug enable value.
1 DBGEN_SEL_STATUS RO 0 Debug enable selector value.
0 DBGEN_I_STATUS RO DBGENINa Debug enable value.

The following table lists the Secure Debug Configuration Set register bits.

Table 3-68 SECDBGSET register

Bits Name Access Reset value Description
[31:8] Reserved RO 0x0 Reserved
7 SPNIDEN_SEL_SET WO 0 Secure privilege non-invasive debug enable selector set control.
6 SPNIDEN_I_SET WO 0 Secure privilege non-invasive debug enable set control.
5 SPIDEN_SEL_SET WO 0 Secure privilege invasive debug enable selector set control.
4 SPIDEN_I_SET WO 0 Secure privilege invasive debug enable set control.
3 NIDEN_SEL_SET WO 0 Non-invasive debug enable selector set control.
2 NIDEN_I_SET WO 0 Non-invasive debug enable set control.
1 DBGEN_SEL_SET WO 0 Debug enable selector set control.
0 DBGEN_I_SET WO 0 Debug enable set control.

The following table lists the Secure Debug Configuration Clear register bits.

Table 3-69 SECDBGCLR register

Bits Name Access Reset value Description
[31:8] Reserved RO 0x0 Reserved
7 SPNIDEN_SEL_CLR WO 0 Secure privilege non-invasive debug enable selector clear control.
6 SPNIDEN_I_CLR WO 0 Secure privilege non-invasive debug enable clear control.
5 SPIDEN_SEL_CLR WO 0 Secure privilege invasive debug enable selector clear control.
4 SPIDEN_I_CLR WO 0 Secure privilege invasive debug enable clear control.
3 NIDEN_SEL_CLR WO 0 Non-invasive debug enable selector clear control.
2 NIDEN_I_CLR WO 0 Non-invasive debug enable clear control.
1 DBGEN_SEL_CLR WO 0 Debug enable selector clear control.
0 DBGEN_I_CLR WO 0 Debug enable clear control.

SCSECCTRL

The System Control Security Controls provide register bits to configure the Certificate access path and the Secure Configuration lock of this register block.

nPORESETAON resets the register.

Table 3-70 SCSECCTRL register

Bits Name Access Reset value Description
[31:18] Reserved RO 0x0 -
17 CERTREADENABLED RO 0

This bit indicates whether the certification read access is enabled:

1 = Certification read access is enabled.

0 = Certification read access is disabled.

This bit is also set to 0 when:

  • The PD_DEBUG power domain is in the OFF state.
  • CERTDISABLED == 1.
16 CERTDISABLED RO 0

This bit indicates whether the certification write path is disabled:

1 = Certification write path is disabled.

0 = Certification write path is enabled.

This bit is also set to 1 whenever the PD_DEBUG power domain is in the OFF state.

[15:3] Reserved RO 0x0 -
2 SCSECCFGLOCK Write 1 to set. 0

Control to disable writes to security-related control registers in this register block.

When set to 1, writes to SECDBGSET, SECDBGCLR, INITSVTOR0, and INITSVTOR1 are ignored.

The bit is only cleared to zero by a power-on reset.

1 CERTREADEN RW 0

Control to enable read access on the certification path:

1 = Enables read access on the certification path, if CERTDISABLE == 0.

0 = Disables read access on the certification path.

0 CERTDISABLE Write 1 to set. 0

Set to 1, to disable the certification path.

This bit can also be set to 1 by:

  • Driving CERTDISABLEEXT HIGH.
  • Turning PD_DEBUG OFF.
  • Changing PD_CPU0CORE power domain from ON.

The bit is only cleared to zero by a power-on reset.

FCLK_DIV

The Fast Clock Divider register allows software to configure the divider ratio that generates FCLK from MAINCLK. After writing to the FCLKDIV field, always check that the new clock divider ratio has been applied by reading it back on FCLKDIV_CUR before doing any other operations.

nPORESETAON resets the register.

Table 3-71 FCLK_DIV register

Bits Name Access Reset value Description
[31:21] Reserved RO 0x0 -
[20:16] FCLKDIV_CUR RO 0x0

Clock Divider Current Value. This field returns the currently selected clock divider value FCLKDIV used to generate FCLK from MAINCLK.

The clock divider setting is the value of FCLKDIV + 1. For example, setting a value of 0 indicates a divider value of 1.

[15:5] Reserved RO 0x0 -
[4:0] FCLKDIV RW FCLKDIV_RST

FCLK from MAINCLK Clock Divider Ratio Request.

The clock divider setting is the value of FCLKDIV + 1. For example, setting a value of 0 indicates a divider value of 1.

SYSCLK_DIV

The System Clock Divider register allows software to configure the divider ratio that generates SYSCLK from FCLK.

After writing to the SYSCLKDIV field, always check that the new clock divider ratio has been applied by reading it back on SYSCLKDIV_CUR before doing any other operations.

nPORESETAON resets the register.

Table 3-72 System Clock Divider register

Bits Name Access Reset value Description
[31:21] Reserved RO 0x0 -
[20:16] SYSCLKDIV_CUR RO 0x0

Clock Divider Current Value. This field returns the currently selected clock divider value SYSCLKDIV used to generate SYSCLK from FCLK.

The clock divider setting is the value of SYSCLKDIV + 1. For example, setting a value of 0 indicates a divider value of 1.

[15:5] Reserved RO 0x0 -
[4:0] SYSCLKDIV RW SYSCLKDIV_RST

SYSCLK from FCLK Clock Divider Ratio Request.

The clock divider setting requested is the value of SYSCLKDIV + 1. For example, setting a value of 0 indicates a divider value of 1.

CLOCK_FORCE

The Clock Force register allows software to override dynamic clock gating that might be implemented in the system and keep each clock running.

Note:

Clock force signals do not apply to clock gates that compliment power gating. Instead, they are applied to hierarchical dynamic clock gating within the system. Forcing a clock ON can reduce the latency that is incurred as a result of dynamic clock control, but can also increase the dynamic power consumption of the system.

All clock force default values are set to 1 at reset. This allows the system to boot in case any hierarchical dynamic clock control implementation is non-functional. You must clear the associated clock force register bit to enable hierarchical dynamic clock control for each clock domain.

nPORESETAON resets the register.

Table 3-73 CLOCK_FORCE register

Bits Name Access Reset value Description
[31:11] Reserved RO 0 -
10 BCRYPTOSPIKCLK_FORCE RW 1 Force BCRYPTOSPIKCLK to run when set to 1.
9 CPUDEBUGPIKCLK_FORCE RW 1 Force CPUDEBUGPIKCLK to run when set to 1.
8 FCLKHINTGATE_ENABLE RW 0

Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF.

Clear this bit to 0 to improve SRAM3 access latency at the cost of increased power consumption.

7 CRYPTOSYSCLK_FORCE RW 1 Force all CryptoCell clocks to run when set to 1.
6 CPUFCLK_FORCE RW 1 Force all CPU FCLK to run when set to 1.
5 CPUSYSCLK_FORCE RW 1 Force all CPU SYSCLK to run when set to 1.
4 SRAMFCLK_FORCE RW 1 Force SRAM Local FCLK to run when set to 1.
3 SRAMSYSCLK_FORCE RW 1 Force SRAM Local SYSCLK to run when set to 1.
2 SYSFCLK_FORCE RW 1 Force Base element Local FCLK to run when set to 1.
1 SYSSYSCLK_FORCE RW 1 Force Base element Local SYSCLK to run when set to 1.
0 MAINCLK_FORCE RW 1 Force MAINCLK to run when set to 1.

RESET_SYNDROME

This register stores the reason for the last reset event.

The register is cleared by nPORESET input or by software writing zeros to each bit to clear them.

Writing HIGH to a bit results in that bit maintaining its previous value.

Note:

LOCKUP0 and LOCKUP1 do not generate reset, but when set to 1, indicate that a processor has locked-up and could be a precursor to another reset event, but Power-on reset, which sets the register to reset value, for example a watchdog timer reset request.

Table 3-74 RESET_SYNDROME register

Bits Name Access Reset value Description
[31:10] Reserved RO 0x0  
9 SWRESETREQ Write 0 to clear. 0x0 Software Reset Request.
8 RESETREQ Write 0 to clear. 0x0 External Reset Request.
7 LOCKUP1 Write 0 to clear. 0x0 CPU 1 Lock-up Status.
6 LOCKUP0 Write 0 to clear. 0x0 CPU 0 Lock-up Status.
5 SYSRSTREQ1 Write 0 to clear. 0x0 CPU 1 System Reset Request.
4 SYSRSTREQ0 Write 0 to clear. 0x0 CPU 0 System Reset Request.
3 S32KWD Write 0 to clear. 0x0 Watchdog on the S32KCLK clock.
2 SWD Write 0 to clear. 0x0 Secure watchdog.
1 NSWD Write 0 to clear. 0x0 Non-secure watchdog.
0 PoR Write 0 to clear. 0x1 Power-on.

RESET_MASK

The RESET_MASK register allows software to control which reset sources are merged to generate the system-wide Warm reset, nSYSRESETAON, or the nPORESETAON signal.

Set each bit to HIGH to enable each source. The nPORESETAON input resets the register.

Note:

Each of these mask bits, if cleared, not only prevents the reset source generating the reset, it also prevents the associated RESET_SYNDROME register bit from recording the event.

Table 3-75 RESET_MASK register

Bits Name Access Reset value Description
[31:6] Reserved RO 0x0 Reserved.
5 SYSRSTREQ1_EN RW SYSRSTREQ1_EN_RST Enable Merging CPU 1 System Reset Request.
4 SYSRSTREQ0_EN RW SYSRSTREQ0_EN_RST Enable Merging CPU 0 System Reset Request.
[3:2] Reserved RO 0x0 Reserved.
1 NSWD_EN RW 0x0 Enable Non-Secure Watchdog Reset.
0 Reserved RO 0x0 Reserved.

SWRESET

The SWRESET register allows software to request a System reset. This register is reset by nPORESETAON.

Table 3-76 SWRESET register

Bits Name Access Reset value Description
[31:10] Reserved RO 0x0 Reserved.
9 SWRESETREQ WO 0x0 Software Reset Request. Set to HIGH to request a system Cold reset.
[8:0] Reserved RO 0x0 Reserved.

GRETREG

The General Purpose Retention Register provides 16 bits of retention register for general storage, especially through power down of the rest of the system. nPORESETAON resets this register.

Table 3-77 GRETREG register

Bits Name Access Reset value Description
[31:16] Reserved RO - Reserved.
[15:0] GRETREG RW 0x0 General Purpose Retention Register.

INITSVTOR0, INITSVTOR1

This contains the value of the Secure Vector table offset address (VTOR_STBLOFF[31:7]), for CPUn.

The reset value is set by the static configuration signals INITSVTORn_RST from the top level.

Register INITSVTOR0 is connected to the CPU0 element, and INITSVTOR1 is connected to the CPU1 element. If CPU 1 does not exist, this register is RAZ/WI.

These registers are reset by nPORESETAON only.

The following tables show how the same bit assignments apply for both the INITSVTOR0 and INITSVTOR1 registers.

Table 3-78 INITSVTOR0 register

Bits Name Access Reset value Description
[31:7] INITSVTOR0 RW INITSVTOR0_RST[31:7] Default Secure Vector table offset at reset for CPU 0.
[6:0] Reserved RO - Reserved.

Table 3-79 INITSVTOR1 register

Bits Name Access Reset value Description
[31:7] INITSVTOR1 RW INITSVTOR1_RST[31:7] Default Secure Vector table offset at reset for CPU 1.
[6:0] Reserved RO - Reserved.

CPUWAIT

This register provides controls to force each processor to wait after reset rather than boot immediately. This allows another entity in the expansion system or the debugger to access the system before the CPU booting. nPORESETAON resets this register.

Table 3-80 CPUWAIT register

Bits Name Access Reset value Description
[31:2] Reserved RO - Reserved.
1 CPU1WAIT RW CPU1WAIT_RST

CPU 1 waits at boot:

  • 0: boot normally
  • 1: wait at boot.

If CPU 1 does not exist, this field is RAZ/WI.

From reset, this bit also controls if CPU 0 powers up.

  • 1: Do not power-up
  • 0: Power-up.
0 CPU0WAIT RW CPU0WAIT_RST

CPU 0 waits at boot:

  • 0: boot normally.
  • 1: wait at boot.

From reset, this bit also controls if CPU 1 powers up.

  • 1: Do not power-up
  • 0: Power-up.

NMI_ENABLE

This register provides controls to enable, or disable, internally or externally generated Non-Maskable Interrupt sources from generating an NMI interrupt on each core. This allows a processor to take control of all internal NMI interrupt sources and mask external NMI interrupts, if necessary.

This register is reset by nPORESETAON only and its reset value is defined by configuration parameters.

Table 3-81 NMI_ENABLE register

Bits Name Access Reset value Description
[31:18] Reserved RO - Reserved.
17 CPU1_EXPNMI_ENABLE RW CPU1_EXPNMI_ENABLE_RST CPU1 Externally Sourced NMI Enable. This determines if the top-level pin, CPU1EXPNMI, can raise an NMI interrupt on CPU1:
  • 1, allowed.
  • 0, masked and not allowed.
16 CPU0_EXPNMI_ENABLE RW CPU0_EXPNMI_ENABLE_RST CPU0 Externally Sourced NMI Enable. This determines if the top-level pin, CPU0EXPNMI, can raise an NMI interrupt on CPU0:
  • 1, allowed.
  • 0, masked and not allowed.
[15:2] Reserved RO - Reserved
1 CPU1_INTNMI_ENABLE RW CPU1_INTNMI_ENABLE_RST CPU1 Internally Sourced NMI Enable. This determines if the subsystem internally generated NMI interrupt sources can raise an NMI interrupt on CPU1:
  • 1, allowed.
  • 0, masked and not allowed.
0 CPU0_INTNMI_ENABLE RW CPU0_INTNMI_ENABLE_RST CPU0 Internally Sourced NMI Enable. This determines if the subsystem internally generated NMI interrupt sources can raise an NMI interrupt on CPU0:
  • 1, allowed.
  • 0, masked and not allowed.

WICCTRL

The WIC Control register allows software to perform the WIC Enable handshake for each individual processor. This register is reset by nWARMRESETAON.

Table 3-82 WICCTRL register

Bits Name Access Reset value Description
[31:18] Reserved RO 0x0 Reserved
17 CPU1WICRDY RO 0x0 CPU 1 WIC Enable Acknowledge. If CPU 1 does not exist, this field is RAZ/WI.
16 CPU0WICRDY RO 0x0 CPU 0 WIC Enable Acknowledge.
[15:10] Reserved RO 0x0 Reserved
9 CPU1WICEN_CLR WO 0x0 CPU 1 WIC Enable Request Clear. Write 1 to clear CPU1WICEN_STATUS to LOW. If CPU 1 does not exist, this field is RAZ/WI.
8 CPU0WICEN_CLR WO 0x0 CPU 0 WIC Enable Request Clear. Write 1 to clear CPU0WICEN_STATUS to LOW.
[7:6] Reserved RO 0x0 Reserved
5 CPU1WICEN_SET WO 0x0 CPU 1 WIC Enable Request Set. Write 1 to set CPU1WICEN_STATUS to HIGH. If CPU 1 does not exist, this field is RAZ/WI.
4 CPU0WICEN_SET WO 0x0 CPU 0 WIC Enable Request Set. Write 1 to set CPU0WICEN_STATUS to HIGH.
[3:2] Reserved RO 0x0 Reserved
1 CPU1WICEN_STATUS RO 0x0 CPU 1 WIC Enable Request Status. Set to HIGH by writing 1 to CPU1WICEN_SET to request enabling of the CPU1 WIC. If CPU 1 does not exist, this field is RAZ/WI.
0 CPU0WICEN_STATUS RO 0x0 CPU 0 WIC Enable Request Status. Set to HIGH by writing 1 to CPU0WICEN_SET to request enabling of the CPU0 WIC.

EWCTRL

The External Wakeup Control register allows software to perform handshake with the External Wakeup Controllers that is associated with each individual processor to support waking the associated core when it is fully powered down.

This register is reset by nWARMRESETAON.

Table 3-83 External Wakeup Control register

Bits Name Access Reset value Description
[31:10] Reserved RO 0x0 Reserved
9 EWC1EN_CLR WO 0x0

External Wakeup Controller 1 Clear.

Writing 1 to this bit clears EWC1EN_STATUS. This field always returns 0 when read. If CPU 1 does not exist, this field is RAZ/WI.

8 EWC0EN_CLR WO 0x0

External Wakeup Controller 0 Clear.

Writing 1 to this bit clears EWC1EN_STATUS. This field always returns 0 when read. If CPU 1 does not exist, this field is RAZ/WI.

[7:6] Reserved RO 0x0 Reserved
5 EWC1EN_SET WO 0x0

External Wakeup Controller 1 Set.

Writing 1 to this bit sets EWC1EN_STATUS. This field always returns 0 when read. If CPU 1 does not exist, this field is RAZ/WI.

4 EWC0EN_SET WO 0x0

External Wakeup Controller 0 Set.

Writing 1 to this bit sets EWC0EN_STATUS. This field always returns 0 when read. If CPU 0 does not exist, this field is RAZ/WI.

[3:2] Reserved RO 0x0 Reserved
1 EWC1EN_STATUS RO 0x0

External Wakeup Controller 1 Enable.

If HIGH, on entering Deepsleep with the WIC enabled, the External Wakeup Controller starts the process of holding interrupts that might arrive when CPU 1 is powered down and, depending on the interrupt mask, attempt to wake CPU 1. If CPU 1 does not exist, this field is RAZ/WI.

0 EWC0EN_STATUS RO 0x0

External Wakeup Controller 0 Enable.

If HIGH, on entering Deepsleep with the WIC enabled, the External Wakeup Controller , starts the process of holding interrupts that might arrive when CPU 0 is powered down and, depending on the interrupt mask, attempt to wake CPU 0.

PDCM_PD_SYS_SENSE

The Power Dependency Control Matrix System Power domain (PD_SYS) Sensitivity register is used to define what keeps the PD_SYS domain awake. This register is reset by nWARMRESETAON.

Table 3-84 Power Dependency Control Matrix System Power Domain Sensitivity register

Bits Name Access Reset value Description
[31:20] Reserved RO 0x0 Reserved.
19 S_PD_EXP3_IN RW 0x0 Enable PDEXPIN[3] signal sensitivity.
18 S_PD_EXP2_IN RW 0x0 Enable PDEXPIN[2] signal sensitivity.
17 S_PD_EXP1_IN RW 0x0 Enable PDEXPIN[1] signal sensitivity.
16 S_PD_EXP0_IN RW 0x0 Enable PDEXPIN[0] signal sensitivity.
[15:13] Reserved RO 0x0 Reserved.
12 S_PD_CRYPTO_ON RO 0x1 Tied to HIGH. PD_SYS always tries to stay ON if S_PD_CRYPTO_ON is ON.
[11:7] Reserved RO 0x0 Reserved.
6 S_PD_SRAM3_ON RO 0x1 Tied to HIGH. PD_SYS always tries to stay ON if SRAM3 power domain is ON.
5 S_PD_SRAM2_ON RO 0x1 Tied to HIGH. PD_SYS always tries to stay ON if SRAM2 power domain is ON.
4 S_PD_SRAM1_ON RO 0x1 Tied to HIGH. PD_SYS always tries to stay ON if SRAM1 power domain is ON.
3 S_PD_SRAM0_ON RO 0x1 Tied to HIGH. PD_SYS always tries to stay ON if SRAM0 power domain is ON.
2 S_PD_CPU1CORE_ON RO 0x1 Tied to HIGH. PD_SYS always tries to stay ON if PD_CPU1CORE is ON.
1 S_PD_CPU0CORE_ON RO 0x1 Tied to HIGH. PD_SYS always tries to stay ON if PD_CPU0CORE is ON.
0 S_PD_SYS_ON RW 0x1 Enable PD_SYS ON Sensitivity. Set HIGH to keep PD_SYS awake after powered ON.

PDCM_PD_SRAM<N>_SENSE

The Power Dependency Control Matrix SRAM<N> Power domain (PD_SRAM) Sensitivity registers are used to define what keeps each of the PD_SRAM<N> power domains awake, where <n> is 0-3.

This register is reset by nWARMRESETAON.

Table 3-85 PDCM_PD_SRAM0_SENSE registers

Bits Name Access Reset value Description
[31:20] Reserved RO 0x0 Reserved.
19 S_PD_EXP3_IN RW 0x0 Enable PDEXPIN[3] signal sensitivity.
18 S_PD_EXP2_IN RW 0x0 Enable PDEXPIN[2] signal sensitivity.
17 S_PD_EXP1_IN RW 0x0 Enable PDEXPIN[1] signal sensitivity.
16 S_PD_EXP0_IN RW 0x0 Enable PDEXPIN[0] signal sensitivity.
[15:13] Reserved RO 0x0 Reserved.
12 S_PD_CRYPTO_ON RO 0x0 Tied to LOW. Ignores PD_CRYPTO ON state.
[11:7] Reserved RO 0x0 Reserved.
6 S_PD_SRAM3_ON RO 0x0 Tied LOW. Ignores PD_SRAM3 ON state.
5 S_PD_SRAM2_ON RO 0x0 Tied LOW. Ignores PD_SRAM2 state.
4 S_PD_SRAM1_ON RO 0x0 Tied LOW. Ignores PD_SRAM1 state.
3 S_PD_SRAM0_ON RW 0x0 Enable sensitivity to PD_SRAM0 ON state.
2 S_PD_CPU1CORE_ON RW 0x0 Enable sensitivity to PD_CPU1CORE ON state.
1 S_PD_CPU0CORE_ON RW 0x0 Enable sensitivity to PD_CPU0CORE ON state.
0 S_PD_SYS_ON RW 0x0 Enable sensitivity to PD_SYS ON state.

Table 3-86 PDCM_PD_SRAM1_SENSE registers

Bits Name Access Reset value Description
[31:20] Reserved RO 0x0 Reserved.
19 S_PD_EXP3_IN RW 0x0 Enable PDEXPIN[3] signal sensitivity.
18 S_PD_EXP2_IN RW 0x0 Enable PDEXPIN[2] signal sensitivity.
17 S_PD_EXP1_IN RW 0x0 Enable PDEXPIN[1] signal sensitivity.
16 S_PD_EXP0_IN RW 0x0 Enable PDEXPIN[0] signal sensitivity.
[15:13] Reserved RO 0x0 Reserved.
12 S_PD_CRYPTO_ON RO 0x0 Tied to LOW. Ignores PD_CRYPTO.
[11:7] Reserved RO 0x0 Reserved.
6 S_PD_SRAM3_ON RO 0x0 Tied LOW. Ignores PD_SRAM3 state.
5 S_PD_SRAM2_ON RO 0x0 Tied LOW. Ignores PD_SRAM2 state.
4 S_PD_SRAM1_ON RW 0x0 Enable sensitivity to PD_SRAM1.
3 S_PD_SRAM0_ON RO 0x0 Tied LOW. Ignores PD_SRAM0 state.
2 S_PD_CPU1CORE_ON RW 0x0 Enable sensitivity to PD_CPU1CORE.
1 S_PD_CPU0CORE_ON RW 0x0 Enable sensitivity to PD_CPU0CORE.
0 S_PD_SYS_ON RW 0x0 Enable sensitivity to PD_SYS.

Table 3-87 PDCM_PD_SRAM2_SENSE registers

Bits Name Access Reset value Description
[31:20] Reserved RO 0x0 Reserved.
19 S_PD_EXP3_IN RW 0x0 Enable PDEXPIN[3] signal sensitivity.
18 S_PD_EXP2_IN RW 0x0 Enable PDEXPIN[2] signal sensitivity.
17 S_PD_EXP1_IN RW 0x0 Enable PDEXPIN[1] signal sensitivity.
16 S_PD_EXP0_IN RW 0x0 Enable PDEXPIN[0] signal sensitivity.
[15:13] Reserved RO 0x0 Reserved.
12 S_PD_CRYPTO_ON RO 0x0 Tied to LOW. Ignores PD_CRYPTO.
[11:7] Reserved RO 0x0 Reserved.
6 S_PD_SRAM3_ON RO 0x0 Tied LOW. Ignores PD_SRAM3 state.
5 S_PD_SRAM2_ON RW 0x0 Enable sensitivity to PD_SRAM2.
4 S_PD_SRAM1_ON RO 0x0 Tied LOW. Ignores PD_SRAM1 state.
3 S_PD_SRAM0_ON RO 0x0 Tied LOW. Ignores PD_SRAM0 state.
2 S_PD_CPU1CORE_ON RW 0x0 Enable sensitivity to PD_CPU1CORE.
1 S_PD_CPU0CORE_ON RW 0x0 Enable sensitivity to PD_CPU0CORE.
0 S_PD_SYS_ON RW 0x0 Enable sensitivity to PD_SYS.

Table 3-88 PDCM_PD_SRAM3_SENSE registers

Bits Name Access Reset value Description
[31:20] Reserved RO 0x0 Reserved.
19 S_PD_EXP3_IN RW 0x0 Enable PDEXPIN[3] signal sensitivity.
18 S_PD_EXP2_IN RW 0x0 Enable PDEXPIN[2] signal sensitivity.
17 S_PD_EXP1_IN RW 0x0 Enable PDEXPIN[1] signal sensitivity.
16 S_PD_EXP0_IN RW 0x0 Enable PDEXPIN[0] signal sensitivity.
[15:13] Reserved RO 0x0 Reserved.
12 S_PD_CRYPTO_ON RO 0x0 Tied to LOW. Ignores PD_CRYPTO.
[11:7] Reserved RO 0x0 Reserved.
6 S_PD_SRAM3_ON RW 0x0 Enable sensitivity toPD_SRAM3.
5 S_PD_SRAM2_ON RO 0x0 Tied LOW. Ignores PD_SRAM2 state.
4 S_PD_SRAM1_ON RO 0x0 Tied LOW. Ignores PD_SRAM1 state.
3 S_PD_SRAM0_ON RO 0x0 Tied LOW. Ignores PD_SRAM0 state.
2 S_PD_CPU1CORE_ON RW 0x0 Enable sensitivity to PD_CPU1CORE.
1 S_PD_CPU0CORE_ON RW 0x0 Enable sensitivity to PD_CPU0CORE.
0 S_PD_SYS_ON RW 0x0 Enable sensitivity to PD_SYS.

PDCM_PD_CRYPTO_SENSE

The Power Dependency Control Matrix CryptoCell Power domain (PD_CRYPTO) Sensitivity register defines what keeps the PD_CRYPTO domains awake.

This register is reset by nWARMRESETAON.

Note:

  • The power domain cannot be configured to be sensitive to other power domain power states.
  • The CryptoCell power domain cannot be configured to be sensitive to other power domain power states, and you can only perform static power control of this domain through the PD_CRYPTO Power Policy Unit.

Table 3-89 PDCM_PD_CRYPTO_SENSE register

Bits Name Access Reset value Description
[31:20] Reserved RO 0x0 Reserved.
19 S_PD_EXP3_IN RO 0x0 Tied LOW. Ignores the PDEXPIN[3] signal.
18 S_PD_EXP2_IN RO 0x0 Tied LOW. Ignores the PDEXPIN[2] signal.
17 S_PD_EXP1_IN RO 0x0 Tied LOW. Ignores the PDEXPIN[1] signal.
16 S_PD_EXP0_IN RO 0x0 Tied LOW. Ignores the PDEXPIN[0] signal.
[15:13] Reserved RO 0x0 Reserved.
12 S_PD_CRYPTO_ON RO 0x1 Tied LOW. Ignores PD_CRYPTO.
[11:7] Reserved RO 0x0 Reserved.
6 S_PD_SRAM3_ON RO 0x0 Tied LOW. Ignores PD_SRAM3 state.
5 S_PD_SRAM2_ON RO 0x0 Tied LOW. Ignores PD_SRAM2 state.
4 S_PD_SRAM1_ON RO 0x0 Tied LOW. Ignores PD_SRAM1 state.
3 S_PD_SRAM0_ON RO 0x0 Tied LOW. Ignores PD_SRAM0 state.
2 S_PD_CPU1CORE_ON RO 0x0 Tied LOW. Ignores PD_CPU1CORE state.
1 S_PD_CPU0CORE_ON RO 0x0 Tied LOW. Ignores PD_CPU0CORE state.
0 S_PD_SYS_ON RO 0x0 Tied LOW. Ignores PD_SYS.
a DBGENIN, NIDENIN, SPIDENIN, and SPNIDENIN are input signals on the Debug Authentication Interface. See A.4.7 Debug authentication interface.
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