3.4.6 Secure Privilege Control Block

The Secure Privilege Control Block implements program-visible states that allow software to control security gating units within the design.

Writes to the registers must be 32 bits wide. Attempted byte and halfword writes are ignored.

Reads are only permitted from Secure privileged accesses. nWARMRESETSYS resets all the registers, which reside in the PD_SYS power domain.

The register block base address is 0x5008_0000. The following table lists the privilege control registers.

Table 3-31 Summary of Secure Privilege Control registers

Offset Name Access Reset value Description
0x000 SPCSECCTRL RW 0x0 Secure Privilege Controller Secure Configuration Control register.
0x004 BUSWAIT RW Parameterized Bus Access wait control after reset.
0x008 Reserved - 0x0 Reserved.
0x010 SECRESPCFG RW 0x0 Security Violation Response Configuration register.
0x014 NSCCFG RW 0x0 Non Secure Callable Configuration for IDAU.
0x018 Reserved - 0x0 Reserved.
0x01C SECMPCINTSTATUS RO 0x0 Secure MPC Interrupt Status.
0x020 SECPPCINTSTAT RO 0x0 Secure PPC Interrupt Status.
0x024 SECPPCINTCLR WO 0x0 Secure PPC Interrupt Clear.
0x028 SECPPCINTEN RW 0x0 Secure PPC Interrupt Enable.
0x02C Reserved - 0x0 Reserved.
0x030 SECMSCINTSTAT RO 0x0 Secure MSC Interrupt Status.
0x034 SECMSCINTCLR RW 0x0 Secure MSC Interrupt Clear.
0x038 SECMSCINTEN RW 0x0 Secure MSC Interrupt Enable.
0x03C Reserved - 0x0 Reserved.
0x040 BRGINTSTAT RO 0x0 Bridge Buffer Error Interrupt Status.
0x044 BRGINTCLR WO 0x0 Bridge Buffer Error Interrupt Clear.
0x048 BRGINTEN RW 0x0 Bridge Buffer Error Interrupt Enable.
0x04C Reserved - 0x0 Reserved.
0x050 AHBNSPPCO RW 0x0 Non-secure access AHB slave Peripheral Protection Control #0. Defines the Non-secure access settings for peripherals in the Base element.
0x0540x05C Reserved - 0x0 Reserved.
0x060 AHBNSPPCEXP0 RW 0x0

Expansion 0 Non-Secure Access AHB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x064 AHBNSPPCEXP1 RW 0x0

Expansion 1 Non-Secure Access AHB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x068 AHBNSPPCEXP2 RW 0x0

Expansion 2 Non-Secure Access AHB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x06C AHBNSPPCEXP3 RW 0x0

Expansion 3 Non-Secure Access AHB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x070 APBNSPPC0 RW 0x0 Non-secure Access APB slave Peripheral Protection Control #0.
0x074 APBNSPPC1 RW 0x0 Non-secure Access APB slave Peripheral Protection Control #1. This register controls the PPC within the System Control element.
0x0780x07C Reserved - 0x0 Reserved.
0x080 APBNSPPCEXP0 RW 0x0

Expansion 0 Non-Secure Access APB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x084 APBNSPPCEXP1 RW 0x0

Expansion 1 Non-Secure Access APB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x088 APBNSPPCEXP2 RW 0x0

Expansion 2 Non-Secure Access APB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x08C APBNSPPCEXP3 RW 0x0

Expansion 3 Non-Secure Access APB slave Peripheral Protection Control. Each field defines the Non-secure access settings for an associated peripheral:

1: Allow Non-secure access.

0: Disallow Non-secure access.

Resets to 0.

0x090 AHBSPPPC0 RO 0x0 Secure Unprivileged Access AHB slave Peripheral Protection Control #0.
0x0940x09C Reserved - 0x0 Reserved.
0x0A0 AHBSPPPCEXP0 RW 0x0

Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0.

0x0A4 AHBSPPPCEXP1 RW 0x0

Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0.

0x0A8 AHBSPPPCEXP2 RW 0x0

Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0.

0x0AC AHBSPPPCEXP3 RW 0x0

Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0.

0x0B0 APBSPPPC0 RW 0x0 Secure Unprivileged Access APB slave Peripheral. Protection Control #0. This register control the PPC within the Base element.
0x0B4 APBSPPPC1 RW 0x0 Secure Unprivileged Access APB slave Peripheral. Protection Control #1. This register controls the PPC within the System Control element.
0x0B80x0BC Reserved - 0x0 Reserved.
0x0C0 APBSPPPCEXP0 RW 0x0

Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0.

0x0C4 APBSPPPCEXP1 RW 0x0

Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0

0x0C8 APBSPPPCEXP2 RW 0x0

Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0.

0x0CC APBSPPPCEXP3 RW 0x0

Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control. Each field defines the Secure unprivileged access settings for an associated peripheral:

1: Allow Secure unprivileged access.

0: Disallow Secure unprivileged access.

Resets to 0.

0x0D0 NSMSCEXP RO 0x0

Expansion MSC Non-secure Configuration. Each field defines if a Master connected to an Expansion Master Security Controller is Secure or Non-secure:

1: Master is Non-secure,

0: Master is Secure.

0x0D40xFCC Reserved - 0x0 Reserved
0xFD0 PID4 RO 0x0000_0004 Peripheral ID 4
0xFD4 PID5 RO 0x0 Reserved
0xFD8 PID6 RO 0x0 Reserved
0xFDC PID7 RO 0x0 Reserved
0xFE0 PID0 RO 0x0000_0052 Peripheral ID 0
0xFE4 PID1 RO 0x0000_00B8 Peripheral ID 1
0xFE8 PID2 RO 0x0000_000B Peripheral ID 2
0xFEC PID3 RO 0x0 Peripheral ID 3
0xFF0 CID0 RO 0x0000_000D Component ID 0
0xFF4 CID1 RO 0x0000_00F0 Component ID 1
0xFF8 CID2 RO 0x0000_0005 Component ID 2
0xFFC CID3 RO 0x0000_00B1 Component ID 3

SPCSECCTRL

The Security Privilege Controller Security Configuration Control register implements the security lock register.

Table 3-32 SPCSECCTRL register

Bits Name Access Reset value Description
[31:1] Reserved RO 0x0 Reserved.
0 SPCSECCFGLOCK Write one to set. 0b0

Set to 1 to disable writes to security-related control registers in the Secure Privilege Control register block.

After being set to 1, it can no longer be cleared to zero except by reset or the base system powering down.

Registers that can no longer be modified when SPCSECCFGLOCK is set to 1 are:

  • NSCCFG
  • AHBNSPPC0
  • AHBNSPPCEXP<N>
  • APBNSPPC0
  • APBNSPPC1
  • APBNSPPCEXP<N>
  • AHBSPPPC0
  • AHBSPPPCEXP<N>
  • APBSPPPC0
  • APBSPPPC1
  • APBSPPPCEXP<N>
  • NSMSCEXP.

BUSWAIT

The Bus Access Wait register allows software to gate access entering the Base element from specific masters in the system. This causes them to stall so that the processor can complete the configuration of the MPCs or other Security registers in the system before the stalled accesses commences.

Table 3-33 BUSWAIT register

Bits Name Access Reset value Description
[31:17] Reserved RO - Reserved
16 ACC_WAITN_STATUS RW 0b0

This status register indicates the status of any gating units that are used to block bus access to the system:

1: allow access.

0: block access.

This register reflects the values on ACCWAITNSTATUS.

[15:1] Reserved RO - Reserved
0 ACC_WAITN RW ACC_WAITN_RST

Request gating units in the system to block bus access to system:

1: allow access.

0: block access.

This control only affects the ACG in the system that feeds into the main AHB fabric, and it excludes access from both cores. It also drives the output signal ACCWAITn.

SECRESPCFG

The Security Violation Response Configuration register is used to define a slave response to an access that causes security violation on the Bus Fabric.

Table 3-34 SECRESPCFG register

Bits Name Access Reset value Description
[31:1] Reserved RO 0x0 Reserved
0 SECRESPCFG RW 0x0

This field configures the slave response in case of a security violation:

0: Read-Zero Write Ignore

1: bus error

Note:

Some slaves, for example the system MPCs, provide their own control registers to configure their response.

These slaves do not depend on this control bit.

NSCCFG

The Non-secure Callable Configuration register allows software to define callable regions of memory. The register can do this if the Secure Code region is 0x1000_0000 to 0x1FFF_FFFF and the Secure RAM region is 0x3000_0000 to 0x3FFF_FFFF.

Table 3-35 NSCCFG register

Bits Name Access Reset value Description
[31:2] Reserved RO 0x0 Reserved
1 RAMNSC RW 0x0

Configures whether the RAM region (0x3000_0000 to 0x3FFF_FFFF) is Non-secure Callable:

0: Not Non-secure Callable

1: Non-secure Callable.

0 CODENSC RW 0x0

Configures whether the CODE region (0x1000_0000 to 0x1FFF_FFFF) is Non-secure Callable:

0: Not Non-secure Callable

1: Non-secure Callable.

SECMPCINTSTATUS

The interrupt signals from all Memory Protection Controllers (MPC), both within the SSE-200 subsystem and in the expansion logic, are merged and sent to the Cortex®-M33 NVIC on a single interrupt signal.

The Secure MPC Interrupt Status Register therefore provides Secure software with the ability to check which one of the MPCs is causing the interrupt. After the source of the interrupt is identified, you must use the MPC register interface to clear the interrupt.

Table 3-36 SECMPCINTSTATUS register

Bits Name Access Reset value Description
[31:16] S_MPCEXP_STATUS RO 0x0

Interrupt Status for Expansion Memory Protection Controller.

Each bit n shows the status of input signal S_MPCEXP_STATUS[n].

The parameter MPCEXP_DIS defines whether each bit within this register is implemented so that if MPCEXP_DIS[i] = 1 then S_MPCEXP_STATUS[i] is disabled and always reads as zeros.

[15:4] Reserved RO 0x0 Reserved.
3 S_MPCSRAM3_STATUS RO 0x0 Interrupt Status for Memory Protection Controller of SRAM BANK 3. If BANK 3 does not exist, this area is reserved and read as zeros.
2 S_MPCSRAM2_STATUS RO 0x0 Interrupt Status for Memory Protection Controller of SRAM BANK 2. If BANK 2 does not exist, this area is reserved and read as zeros.
1 S_MPCSRAM1_STATUS RO 0x0 Interrupt Status for Memory Protection Controller of SRAM BANK 1. If BANK 1 does not exist, this area is reserved and read as zeros.
0 S_MPCSRAM0_STATUS RO 0x0 Interrupt Status for Memory Protection Controller of SRAM BANK 0.

SECPPCINTSTAT, SECPPCINTCLR, and SECPPCINTEN

When access violations occur on any Peripheral Protection Controller, a level interrupt is raised from a combined interrupt to the Cortex®-M33 NVIC. The PPC Secure PPC Interrupt Status, Clear and Enable Registers allow software to determine the source of the interrupt, clear the interrupt, and enable or disable (mask) the interrupt.

The following table describes the bits that are used in the SECPPCINTSTAT register.

Table 3-37 PPC SECPPCINTSTAT register

Bits Name Access Reset value Description
[31:24] Reserved RO 0x0 Reserved.
[23:20] S_AHBPPCEXP_STATUS RO 0x0 Interrupt Status of Expansion Peripheral Protection Controller for AHB slaves. Each bit n shows the status of input signal S_AHBPPCEXP_STATUS[n].
[19:16] Reserved RO 0x0 Reserved.
[15:8] Reserved RO 0x0 Reserved.
[7:4] S_APBPPCEXP_STATUS RO 0x0 Interrupt Status of Expansion Peripheral Protection Controller for APB slaves. Each bit n shows the status of input signal S_AHBPPCEXP_STATUS[n].
[3:2] Reserved RO 0x0 Reserved.
1 S_APBPPC1PERIP_STATUS RO 0x0 Interrupt Status of Peripheral Protection Controller for APB slaves within the System Control element.
0 S_APBPPC0PERIP_STATUS RO 0x0 Interrupt Status of Peripheral Protection Controller for APB slaves within the Base element.

The following table describes the bits used in the SECPPCINTCLR register.

Table 3-38 SECPPCINTCLR Register

Bits Name Access Reset value Description
[31:24] Reserved RO 0x0 Reserved.
[23:20] S_AHBPPCEXP_CLR WO 0x0 Interrupt Clear of Expansion Peripheral Protection Controller for AHB slaves. Each bit n drives the output signal S_AHBPPCEXP_CLEAR[n]. Write 1 to clear.
[19:16] Reserved RO 0x0 Reserved.
[15:8] Reserved RO 0x0 Reserved.
[7:4] S_APBPPCEXP_CLR WO 0x0 Interrupt Clear of Expansion Peripheral Protection Controller for APB slaves. Each bit n drives the output signal S_APBPPCEXP_CLEAR[n]. Write 1 to clear.
[3:2] Reserved RO 0x0 Reserved.
1 S_APBPPC1PERIP_CLR WO 0x0 Interrupt Clear of Peripheral Protection Controller for APB slaves within the System Control element. Write 1 to clear.
0 S_APBPPC0PERIP_CLR WO 0x0 Interrupt Clear of Peripheral Protection Controller for APB slaves within the Base element. Write 1 to clear.

The following table describes the bits used in the SECPPCINTEN register.

Table 3-39 SECPPCINTEN Register

Bits Name Access Reset value Description
[31:24] Reserved RO 0x0 Reserved
[23:20] S_AHBPPCEXP_EN RW 0x0 Interrupt Enable of Expansion Peripheral Protection Controller for AHB slaves. Each bit n Enables or disable an interrupt from S_AHBPPCEXP_STATUS[n]. Write 1 to enable and 0 to mask this interrupt source.
[19:16] Reserved RO 0x0 Reserved
[15:8] Reserved RO 0x0 Reserved
[7:4] S_APBPPCEXP_EN RW 0x0 Interrupt Enable of Expansion Peripheral Protection Controller for APB slaves. Each bit n Enables or disable an interrupt from S_APBPPCEXP_STATUS[n]. Write 1 to enable and 0 to mask this interrupt source.
[3:2] Reserved RO 0x0 Reserved
1 S_APBPPC1PERIP_EN RW 0x0 Interrupt Enable of Peripheral Protection Controller for APB slaves within the System Control element. Write 1 to enable and 0 to mask this interrupt source.
0 S_APBPPC0PERIP_EN RW 0x0 Interrupt Enable of Peripheral Protection Controller for APB slaves within the Base element. Write 1 to enable and 0 to mask this interrupt source.

SECMSCINTSTAT, SECMSCINTCLR, and SECMSCINTEN

When security violation occurs at any Master Security Controller (MSC) in the SSE-200 and also in the expansion logic, an interrupt is raised from a combined interrupt to the CPU NVIC.

The Secure MSC Interrupt Status Clear Register and Enable Register allow software to determine the source of the interrupt, clear the interrupt, and enable or disable (mask) the interrupt.

The following table describes the bits used in the SECMSCINTSTAT register.

Table 3-40 SECMSCINTSTAT register

Bits Name Access Reset value Description
[31:16] S_MSCEXP_STATUS RO 0x0

Interrupt Status for Expansion MSC. Each bit n shows the status of input signal SMSCEXPSTATUS[n].

The parameter MSCEXP_DIS defines if each bit within this register is implemented so that if MSCEXP_DIS[i] = 1, then S_MSCEXP_STATUS[i] is disabled and always reads as zeros.

[15:1] Reserved RO 0x0 Reserved.
0 Reserved RO 0x0 Reserved.

The following table describes the bits used in the SECMSCINTCLR register.

Table 3-41 SECMSCINTCLR Register

Bits Name Access Reset value Description
[31:16] S_MSCEXP_CLR WO 0x0

Interrupt Clear for Expansion MSC. Each bit n drives the output signal SMSCEXPCLEAR[n].

The parameter MSCEXP_DIS defines if each bit within this register is implemented so that if MSCEXP_DIS[i] = 1, then S_MSCEXP_CLR[i] is disabled and any writes to it are ignored.

[15:1] Reserved RO 0x0 Reserved.
0 Reserved RO 0x0 Reserved.

The following table describes the bits used in the SECMSCINTEN register.

Table 3-42 SECMSCINTEN Register

Bits Name Access Reset value Description
[31:16] S_MSCEXP_EN RW 0x0

Interrupt Enable for Expansion MSC. Each bit n enables or disables the input interrupt signal SMSCEXPSTATUS[n].

The parameter MSCEXP_DIS defines if each bit within this register is implemented so that if MSCEXP_DIS[i] = 1, then S_MSCEXP_EN[i] is disabled and any writes to it are ignored.

[15:1] Reserved RO 0x0 Reserved.
0 Reserved RO 0x0 Reserved.

BRGINTSTAT, BRGINTCLR, and BRGINTEN

AHB bus bridges are necessary to handle clock domain crossing.

To improve system performance, some of these bridges are able to buffer write data, and complete a write access on their slave interfaces before any potential error response is received for the write access on their master interfaces. When this occurs, these bridges can raise a combined interrupt to the Cortex-M33 NVIC.

The Bridge Buffer Error Interrupt Status, Clear, and Enable registers allow software to determine source of the interrupt, clear the interrupt, and enable or disable (mask) the interrupt.

Since the secondary processor (CPU 1) can operate at a higher clock frequency, FCLK, compared to the main system SYSCLK, a bridge within the SSE-200 supports a write buffer to improve performance.

The following table describes the bits used in the BRGINTSTAT register.

Table 3-43 BRGINTSTAT register

Bits Name Access Reset value Description
[31:16] BRGEXP_STATUS RO 0x0

Status of the Interrupt Clear of Expansion Bridge Buffer Error Interrupts. Each bit n shows the status of BRGEXPSTATUS[n].

The parameter BRGEXP_DIS defines if each bit within this register is implemented so that if BRGEXP_DIS[i] = 1, then BRGEXP_STATUS[i] is disabled and always reads as zero.

[15:1] Reserved RO 0x0 Reserved
0 BRG_CPU1SYS_STATUS RO 0x0 Interrupt Status of Write Buffer the Bridge Error for the bridge between CPU1 and the System. If CPU 1 does not exist, then this bit is reserved, reading as zero.

The following table describes the bits used in the BRGINTCLR register.

Table 3-44 BRGINTCLR register

Bits Name Access Reset value Description
[31:16] BRGEXP_CLR WO 0x0

Interrupt clear of Expansion Bridge Buffer Error Interrupts. Each bit n drives the output signal BRGEXPCLEAR[n].

The parameter BRGEXP_DIS defines if each bit within this register is implemented so that if BRGEXP_DIS[i] = 1, then BRGEXP_CLR[i] is disabled and any writes to it is ignored.

[15:1] Reserved RO 0x0 Reserved
0 BRG_CPU1SYS_CLR WO 0x0

Interrupt Clear of Write Buffer Bridge Error for Bridge between CPU1 and System.

If CPU 1 does not exist, this register is reserved and any writes to this register are ignored.

The following table describes the bits used in the BRGINTEN register.

Table 3-45 BRGINTEN register

Bits Name Access Reset value Description
[31:17] Reserved RO 0x0 Reserved
[16] BRGEXP_EN RW 0x0

Interrupt Enable of Expansion Bridge Buffer Error Interrupts. Each bit n enables the input interrupt BRGEXPSTATUS[n].

The parameter BRGEXP_DIS defines if each bit within this register is implemented so that if BRGEXP_DIS[i] = 1, then BRGEXP_EN[i] is disabled and any writes to it are ignored.

[15:1] Reserved RO 0x0 Reserved
0 BRG_CPU1SYS_EN WO 0x0

Interrupt Enable of Write Buffer Bridge Error for Bridge between CPU1 and System.

If CPU 1 does not exist, this register is reserved and any writes to this register are ignored.

AHBNSPPC0

The Non-secure Access AHB Slave Peripheral Protection Controller Register allows software to configure if each AHB peripheral that it controls from an AHB PPC is Secure access only or is Non-secure access only.

Each field defines the Secure or Non-secure access setting for an associated peripheral, as follows:

  • 1: Allow Non-secure access only.
  • 0: Allow Secure access only.

SSE-200 does not have an AHB slave interface that needs security configuration support of the PPC. This register is reserved and RAZ/WI.

Table 3-46 AHBNSPPC0 register

Bits Name Access Reset value Description
[31:0] Reserved RO 0x0 Reserved.

AHBNSPPCEXP0, AHBNSPPCEXP1, AHBNSPPCEXP2, and AHBNSPPCEXP3

The Expansion Non-secure Access AHB Slave Peripheral Protection Controller registers 0, 1, 2 and 3 allow software to configure each AHB peripheral that it controls from each AHB PPC that resides in the expansion subsystem outside the SSE-200.

Each field defines the Secure or Non-secure access setting for an associated peripheral, as follows:

  • 1: Allow Non-secure access only.
  • 0: Allow Secure access only.

These controls directly control the expansion signals on the Security Control Expansion interface. All four registers are similar and each register, N where N is from 0-3, are described in the following table.

Table 3-47 AHBNSPPCEXP<N> register

Bits Name Access Reset value Description
[31:16] Reserved RO 0x0 Reserved.
[15:0] AHBNSPPCEXP<N> RW 0x0

Expansion N Non-Secure Access AHB slave Peripheral Protection Control. Each bit n drives the output signal AHBNSPPCEXP<N>[n].

The parameter AHBPPCEXP_DIS<N> defines if each bit within this register is implemented so that if AHBPPCEXP_DIS<N>[i] = 1, AHBNSPPCEXP<N>[i] is disabled, reads as zeros, and any writes to it are ignored.

APBNSPPC0 and APBNSPPC1

A Non-secure Access APB slave Peripheral Protection Control Register allows software to configure if each APB peripheral that it controls from an APB PPC is Secure access only or is Non-secure access only. Each bit defines the Secure or Non-secure access setting for an associated peripheral, as follows:

  • 1: Allow Non-secure access only. Secure access is not allowed.
  • 0: Allow Secure access only. Non-secure access is not allowed.

The APBNSPPC0 register controls peripherals that are in the Base element, while the APBNSPPC1 register controls peripherals that are in the System Control element.

Table 3-48 APBNSPPC0 register

Bits Name Access Reset value Description
[31:5] Reserved RO 0x0 Reserved
4 NS_MHU1 RW 0x0 APB access security setting for MHU 1
3 NS_MHU0 RW 0x0 APB access security setting for MHU 0
2 NS_DTIMER RW 0x0 APB access security setting for DUAL TIMER
1 NS_TIMER1 RW 0x0 APB access security setting for TIMER 1
0 NS_TIMER0 RW 0x0 APB access security setting for TIMER 0

The following table describes the bits used in the APBNSPPC1 register.

Table 3-49 APBNSPPC1 register

Bits Name Access Reset value Description
[31:1] Reserved RO 0x0 Reserved
0 NS_S32K Timer RW 0x0 S32K Timer

AHBSPPPC0

Secure Unprivileged Access AHB Slave Peripheral Protection Controller register allows software to configure if each AHB peripheral that it controls from an AHB PPC is Secure privileged, Secure Access, or if it is allowed Secure Unprivileged access as well. Each field defines this for an associated peripheral, by the following settings:

  • 1: Allow Secure unprivileged and privileged access.
  • 0: Allow Secure privileged access only.

SSE-200 does not have an AHB slave interface that needs security configuration support of the PPC. This register is reserved and RAZ/WI.

Table 3-50 AHBSPPPC0 Register

Bits Name Access Reset value Description
[31:0] Reserved RO 0x0 Reserved

AHBSPPPCEXP0, AHBSPPPCEXP1, AHBSPPPCEXP2, and AHBSPPPCEXP3

The Expansion Secure Privilege Access AHB Slave Peripheral Protection Controller registers 0, 1, 2 and 3 allow software to configure each AHB peripheral that it controls from each AHB PPC. These registers allow Secure privileged Access only or both Secure unprivileged and privlegded access.

Each field defines this access for an associated peripheral, by the following settings:

  • 1: Allow Secure unprivileged and privileged access.
  • 0: Allow Secure privileged access only.

These bits directly control the expansion signals on the Security Control Expansion interface. All four registers are similar and each register N, where N is from 0 to 3, is as described in the following table.

Table 3-51 AHBSPPPCEXP<N> register

Bits Name Access Reset value Description
[31:16] Reserved RO 0x0 Reserved
[15:0] AHBSPPPCEXP<N> RW 0x0

Expansion N Secure Privilege Access AHB slave Peripheral Protection Control. Each bit n drives the output signal AHBPPPCEXP<N>[n] if AHBNSPPCEXP<N>[n] is 0, where N is 0 to 3.

The parameter AHBPPCEXP_DIS<N> defines if each bit within this register is implemented so that if AHBPPCEXP_DIS<N>[i] = 1, AHBSPPPCEXP<N>[i] is disabled, it reads as zeros, and any writes to it are ignored.

APBSPPPC0 and APBSPPPC1

Each APB peripheral controlled by an APB PPC is either Secure privileged access only, or both Secure unprivileged access and Secure privileged access. Each field defines these settings for an associated peripheral by the following:

  • 1: Enable Secure unprivileged and privileged access.
  • 0: Enable Secure privileged access only.

Table 3-52 APBSPPPC0 register

Bits Name Access Reset value Description
[31:5] Reserved RO 0x0 Reserved
4 SP_MHU1 RW 0x0 APB access Secure privileged setting for MHU 1
3 SP_MHU0 RW 0x0 APB access Secure privileged setting for MHU 0
2 SP_DTIMER RW 0x0 APB access Secure privileged setting for DUAL TIMER
1 SP_TIMER1 RW 0x0 APB access Secure privileged setting for TIMER 1
0 SP_TIMER0 RW 0x0 APB access Secure privileged setting for TIMER 0

Table 3-53 APBSPPPC1 Register

Bits Name Access Reset value Description
[31:1] Reserved RO 0x0 Reserved
0 SP_S32KTIMER RW 0x0 APB access Secure privileged setting for S32KCLK Timer

APBSPPPCEXP0, APBSPPPCEXP1, APBSPPPCEXP2, and APBSPPPCEXP3

The Expansion Secure Privilege Access APB Slave Peripheral Protection Controller register 0, 1, 2 and 3 allow software to configure each APB peripheral that it controls from each APB PPC. These reside in the expansion subsystem outside the SSE-200, allowing Secure privileged access only or both Secure unprivileged and privileged access.

Each field defines this for an associated peripheral, by the following settings:

  • 1: Allow Secure unprivileged and privileged access.
  • 0: Allow Secure privileged access only.

These controls directly control the expansion signals on the Security Control Expansion interface. All four registers are similar and each register N, where N is from 0-3, are described in the following table.

Table 3-54 APBSPPPCEXP<N> register

Bits Name Access Reset value Description
[31:16] Reserved RO 0x0 Reserved
[15:0] APBSPPPCEXP<N> RW 0x0

Expansion N Secure Privilege Access APB slave Peripheral Protection Control. Each bit n drives the output signal APB_P_PPCEXP<N>[n] if APBNSPPCEXP<N>[n] is 0, where N is 0 to 3.

The parameter APBPPCEXP_DIS<N> defines if each bit within this register is implemented so that if APBPPCEXP_DIS<N>[i] = 1, APBSPPPCEXP<N>[i] is disabled, it reads as zeros, and any writes to it are ignored.

NSMSCEXP

The Non-secure Expansion Master Security Controller register allows software to configure if each master that is located behind each MSC in the expansion subsystem is a Secure or Non-secure device.

Table 3-55 NSMSCEXP register

Bits Name Access Reset value Description
[31:16] NS_MSCEXP RW 0x0a

Expansion MSC Non-secure Configuration. Each bit n controls the Non-secure configuration of each MSC and drives the signals NS_MSCEXP[n].

0: Master is Secure.

1: Master is Non-secure.

The parameter MSCEXP_DIS<N> defines if each bit within this register is implemented so that if MSCEXP_DIS<N>[i] = 1, NS_MSCEXP[i] is disabled, it reads as zeros, and any writes to it are ignored.

[15:0] Reserved RO 0x0 Reserved
a This reset value means that the expansion master is Secure after reset. If the expansion masters is prevented from accessing the Secure part of the system, use ACCWAITn to gate access until the processor completes security configuration.
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