3.2.1 Memory map overview

A high-level overview of the SSE-200 system memory map is shown in the following figure:

Figure 3-1 SSE-200 Simplified view memory map
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The following table shows the high-level view of the memory map that is defined by SSE-200. This memory map is divided into Secure and Non-secure regions. The memory alternates between Secure and Non-secure regions on 256Mbyte regions, with only a few address areas that are exempt from security mapping because they are related to debug functionality. To provide memory blocks and peripherals that can be mapped either as Secure or Non-secure using software, several address regions are aliased as shown in the following table. Software can then choose to allocate each memory block or peripheral as Secure or Non-secure using protection controllers. The Implementation Defined Attribution Unit (IDAU) region column in the table specifies security for each area along with ID and Non-Secure Callable (NSC) settings for each region. Except when stated, all access to unmapped regions of the memory result in a bus-error response. An exception to that is when accessing unmapped address space within a region taken by a peripheral. The access is Read As Zero and Write Ignored (RAZ/WI). Any accesses that result in security violations, either RAZ/WI or result in a bus error response as defined by the SECRESPCFG register setting. Some regions of memory map are reserved to maintain compatibility with future subsystems. Other areas are mapped to AHB Master Expansion 0 interface and AHB Master Expansion 1 interfaces. All accesses targeting populated SRAM regions within 0x2000_0000 to 0x20FF_FFFF and 0x3000_0000 to 0x30FF_FFFF support exclusive accesses since they implement exclusive access monitoring, provided the accesses are from:

  • The processors.
  • Expansion masters that have their corresponding EXP_SYS_ID_PRESENT bit matching the Master ID set to HIGH.

Exclusive accesses are not supported for other regions implementing within the subsystem. For regions that reside in user expansion areas, the user expansion logic defines exclusive access support.

Note:

If an exclusive access targets regions that do not support exclusive accesses, or have Master IDs that do not have the corresponding top-level parameter EXP_SYS_ID_PRESENT bit set to 1, these accesses are not monitored for exclusive access and might still update their target memory locations regardless of their associated exclusive responses.

The following table lists the main regions in the memory map.

Table 3-1 Memory map overview

ID (alias) Address Size Region name Description IDAU securitya IDAUID IDAU NSC
  From To            
1 (4) 0x0000_0000 0x0DFF_FFFF 224MB Code Memoryb Maps to AHB5 master expansion code interface. NS 0 0
2 (5) 0x0E00_0000 0x0E00_1FFF 8KB NVM codec CryptoCell APB code interface for NVM.
3 0x0E00_2000 0x0FFF_FFFF - Reserved Reserved.
4 (1) 0x1000_0000 0x1DFF_FFFF 224MB Code Memoryb Maps to AHB5 master expansion code interface. S 1 CODENSCd
5 (2) 0x1E00_0000 0x1E00_1FFF 8KB NVM codec CryptoCell APB code interface for NVM.
6 0x1E00_2000 0x1FFF_FFFF - Reserved Reserved.
7 (10) 0x2000_0000 0x20FF_FFFF 16MB Internal SRAM Internal SRAM area. NS 2 0
8 0x2100_0000 0x27FF_FFFF 112MB Reserved Reserved.
9 0x2800_0000 0x2FFF_FFFF 128MB Expansion 0 Maps to AHB5 master expansion 0 interface.
10 (7) 0x3000_0000 0x30FF_FFFF 16MB Internal SRAM Internal SRAM Area. S 3 RAMNSCd
11 0x3100_0000 0x37FF_FFFF 112MB Reserved Reserved.
12 0x3800_0000 0x3FFF_FFFF 128MB Expansion 0 Maps to AHB5 master expansion 0 interface.
13 0x4000_0000 0x4000_FFFF 64KB Base Peripheral Base element peripheral region. NS 4 0
14 (21) 0x4001_0000 0x4001_FFFF 64KB Private CPU CPU element peripheral region.
15 (22) 0x4002_0000 0x4003_FFFF 128KB System Control System Control element peripheral region.
16 0x4004_0000 0x4004_FFFF   Reserved Reserved.
17 0x4005_0000 0x4007_FFFF   Reserved Reserved.
18 0x4008_0000 0x400F_FFFF 512KB Base Peripheral Base element peripheral region.
19 0x4010_0000 0x4FFF_FFFF 255MB Expansion 1 Maps to AHB5 master expansion 1 interface.
20 0x5000_0000 0x5000_FFFF 64KB Base Peripheral Base element peripheral region. S 5 0
21 (14) 0x5001_0000 0x5001_FFFF 64KB Private CPU CPU element peripheral region.
22 (15) 0x5002_0000 0x5003_FFFF 128KB System Control System Control element peripheral region.
23 0x5004_0000 0x5004_FFFF   Reserved Reserved.
24 0x5005_0000 0x5007_FFFF   Reserved Reserved.
25 0x5008_0000 0x500F_FFFF 512KB Base Peripheral Base element peripheral region.
26 0x5010_0000 0x5FFF_FFFF 255MB Expansion 1 Maps to AHB5 master expansion 1 interface.
27 0x6000_0000 0x6FFF_FFFF 256MB Expansion 0 Maps to AHB5 master expansion 0 interface. NS 6 0
28 0x7000_0000 0x7FFF_FFFF 256MB Expansion 0 Maps to AHB5 master expansion 0 interface. S 7 0
29 0x8000_0000 0x8FFF_FFFF 256MB Expansion 1 Maps to AHB5 master expansion 1 interface. NS 8 0
30 0x9000_0000 0x9FFF_FFFF 256MB Expansion 1 Maps to AHB5 master expansion 1 interface. S 9 0
31 0xA000_0000 0xAFFF_FFFF 256MB Expansion 1 Maps to AHB5 master expansion 1 interface. NS A 0
32 0xB000_0000 0xBFFF_FFFF 256MB Expansion 1 Maps to AHB5 master expansion 1 interface. S B 0
33 0xC000_0000 0xCFFF_FFFF 256MB Expansion 1 Maps to AHB5 master expansion 1 interface. NS C 0
34 0xD000_0000 0xDFFF_FFFF 256MB Expansion 1 Maps to AHB5 master expansion 1 interface. S D 0
35 0xE000_0000 0XE00F_FFFF 1MB PPB Private Peripheral Bus. Local to Each processor. Exempt    
36 0xE010_0000 0XEFFF_FFFF 255MB Expansion 1 Maps to AHB5 master expansion 1 interface. NS E 0
37 0xF000_0000 0XF00F_FFFF 1MB System debug System debug. Exempt    
38 0xF010_0000 0XFFFF_FFFF 255MB Expansion 1 Maps to AHB5 master expansion 1 interface. S F 0
a The IDAU security value does not define privileged or unprivileged accessibility. That is defined by the MPC, PPC, or register blocks mapped to each area.
b  Even though these regions are not aliased at the interface, they are expected to be aliased in the expansion system to support Non-secure and Secure shared code memory. In addition you must use Memory Protection Controllers externally to selectively map each block of memory between Secure and Non-secure memory regions.
c This region is reserved and responds with bus error if Crypto element does not exist.
d The IDAU NSC values are defined by registers in the Secure Privilege Control registers.
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