2.5.8 Expansion ports

The following sections describe the different types of AHB5 ports.

AHB slave expansion interfaces

Two expansion AMBA AHB5 slave interfaces are provided to allow the system integrator to add extra bus masters to the system. These interfaces are:

  • AHB5 slave expansion 0 interface.
  • AHB5 slave expansion 1 interface.

Each of these interfaces supports the following features:

  • 32-bit address.
  • 32-bit data width.
  • TrustZone®-Arm®v8‑M security support, with HNONSEC signal.
  • HPROT signal indicates the access property, including if the access is privileged.
  • Exclusive access support to SRAM memory.

AHB5 slave expansion 0 interface can access the entire system memory map. The AHB5 slave expansion 1 interface can access the entire system memory map but it cannot access the AHB5 master expansion code interface and the Crypto code interface. For more information, see the 2.5.3 AHB5 bus matrix.

AHB master expansion interfaces

Two expansion AMBA AHB5 master interfaces are provided to allow the system integrator to add extra slave peripherals to the system. These interfaces are:

  • AHB5 master expansion 0 interface.
  • AHB5 master expansion 1 interface.

The SSE-200 also provides an AHB5 master expansion code interface. This master interface is provided primarily to provide access to code memory.

Each of these interfaces supports the following features:

  • 32-bit address bus for both AHB5 Master Expansion 0 and AHB5 Master Expansion 1 interfaces, with each access providing the full 32-bit address.
  • 29-bit address bus for the AHB5 Master Expansion Code interface.
  • 32-bit data width.
  • TrustZone Security support, with the inclusion of HNONSEC and HPROT signals.
  • Exclusive access support. However, for exclusive accesses to function correctly, the slave memory device in the expansion system that supports exclusive accesses must implement exclusive access monitoring.

Note:

In the expansion system, Arm expects the system integrator to insert a Memory Protection Controller (MPC) on the path to code memory, on the AHB5 Master Expansion Code Interface. The MPC provides security access gating, for the aliased memory region that this interface supports.
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