A.6.1 Top-level signals

The following table lists signals at the top-level of the SSE-200.

Table A-19 SSE-200 top-level signals

Signal name Width Direction Description
LOCKNSVTOR0 1 Input

When HIGH, disables writes to the CPU 0 Non-secure vector table base address register, VTOR_NS.

If not used, tie to LOW.

LOCKNSVTOR1 1 Input

When HIGH, disables writes to the CPU 1 Non-secure vector table base address register, VTOR_NS.

This signal does not exist if CPU 1 does not exist in the system.

If not used, tie to LOW.

LOCKNSMPU0 1 Input

When HIGH, disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn in CPU 0

When HIGH all writes to the registers are ignored.

This signal has no effect if the CPU 0 has been configured without any Non-secure MPU regions.

If not used, tie to LOW.

LOCKNSMPU1 1 Input

When HIGH, disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn in CPU 1

When HIGH, all writes to the registers are ignored.

This signal has no effect if the CPU 1 does not exist or CPU 1 has been configured without any Non-secure MPU regions.

If not used, tie to LOW.

CPU0TRCENA 1 Output

Trace Enable. This signal reflects the setting of the DEMCR.TRCENA bit for CPU0.

It can be used as control signal to enable or disable trace-related functionality outside the subsystem.

CPU1TRCENA 1 Output

Trace Enable. This signal reflects the setting of the DEMCR.TRCENA bit for CPU1.

It can be used as control signal to enable or disable trace-related functionality outside the subsystem.

SYSSYNCHCLAMPREADY 1 Input Synchronous clamping ready status. When LOW, indicates that all clamps, requested by SYSSYNCHCLAMP* signals are applied.
SYSSYNCHCLAMPRETOFFHIGH 1 Output Synchronous clamping enable for outputs to clamp HIGH in OFF or RETENTION states. These are set to HIGH before the PD_SYS domain is isolated and enters OFF/Retention state.
SYSSYNCHCLAMPRETOFFLOW 1 Output Synchronous clamping enable for outputs to clamp LOW in OFF or RETENTION states. These are set to LOW before the PD_SYS domain is isolated and enters OFF/Retention state.
SYSSYNCHCLAMPOFFHIGH 1 Output Synchronous clamping enable for outputs to clamp HIGH only in OFF state. These are set to HIGH before the PD_SYS domain is isolated and enters OFF state.
SYSSYNCHCLAMPOFFLOW 1 Output Synchronous clamping enable for outputs to clamp LOW only in OFF state. These are set to LOW before the PD_SYS domain is isolated and enters OFF state.
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