A.4.1 DAP signals

The following table lists the DAP Access Bus Interface signals which allow an external DAP to access debug logic within the system and to also request for the debug system to wake.

Note:

All signals on this interface, unless stated otherwise, are:
  • Synchronous to DEBUGSYSCLK.
  • Reset by nPORESETDEBUG.
  • In the PD_DEBUG power domain.

Table A-6 DAP Access Buffer signals

Signal name Width Direction Clock domain Description
DAPCADDRS 14 Input DEBUGSYSCLK DAP compressed address bus.
DAPSELS 1 Input DEBUGSYSCLK Select signal generated from the DAP decoder to each AP. This signal indicates that the slave device is selected, and a data transfer is required.
DAPENABLES 1 Input DEBUGSYSCLK DAP enable.
DAPWRITES 1 Input DEBUGSYSCLK When HIGH indicates a DAP write access from DP to AHB-AP. When LOW, indicates a read access.
DAPWDATAS 32 Input DEBUGSYSCLK DAP write data bus.
DAPABORTS 1 Input DEBUGSYSCLK DAP abort.
DAPRDATAS 32 Output DEBUGSYSCLK DAP read data bus.
DAPREADYS 1 Output DEBUGSYSCLK DAP ready.
DAPSLVERRS 1 Output DEBUGSYSCLK DAP error.
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