2.1 About the hardware components

The SSE-200 contains the following hardware components:

  • Two Cortex®-M33 processors:

    • Optional Floating-Point Unit (FPU) and Digital Signal Processor (DSP) extensions (configurable).
    • Embedded Trace Macrocell (ETM).

    For more information, see the Arm® Cortex®-M33 Processor Technical Reference Manual.

  • CoreSight™ debug system with configurable Secure Debug and Trace.
  • Secure AMBA® interconnect:

    • Advanced High Performance Bus (AHB5) Bus Matrix.
    • AHB5 TrustZone® Memory Protection Controller (MPC).
    • AHB5 TrustZone Peripheral Protection Controller (PPC).
    • AHB5 Exclusive Access Monitor (EAM).
    • AHB5 Access Control Gates (ACG).
    • AHB5 to Advanced Peripheral Bus (APB) bridges.
    • Expansion AHB5 master and slave buses (two each).
  • Memory system:

    • AHB5 multi-layer bus matrix.
    • Static memory controllers.
    • Multiple banks of SRAM.

      One bank of SRAM functions as Tightly Coupled Memory (TCM).

    • Instruction caches.
  • Security components:

    • TrustZone CryptoCell-312 (optional).
    • Implementation Defined Attribution Unit (IDAU).
    • Secure expansion ports.
    • System Security Controller.
    • System Controller.
    • Secure debug with debug certificate controlled authentication.
  • APB peripherals with security support:

    • Three general-purpose timers with configurable security. One timer is on the 32KHz domain and two are on the SYSCLK domain.

    • A Cortex-M System Design Kit (CMSDK) dual timer with configurable security.
    • Three Watchdog timers with fixed security. One Secure watchdog is on the 32KHz domain and one Secure and one Non-Secure is on the SYSCLK domain.
    • Two Message Handling Units (MHUs) to facilitate communication between processors.
  • Power-control components:

    • Power Dependency Control Matrix (PDCM).

    • Power Policy Units (PPU).
    • CoreLink™ LPD-500 Low Power Distributor.
    • Wakeup on interrupt from External Wakeup Controllers (EWC) and Wakeup Interrupt Controllers (WIC).
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