1.2.1 Hardware deliverables

The hardware deliverables include the following:

  • SSE-200 Verilog RTL that includes the SSE subsystem proprietary logic, and elements using the CoreLink™ SIE-200 System IP for Embedded, the Cortex®-M0 System Design Kit, and the CoreLink LPD-500 Low Power Distributor.
  • RTL build scripts that automate the process of instantiating a complete subsystem with the licensed options and selected configuration.
  • An Out-of-Box (OoB) RTL testbench that includes test vectors.
  • Static Timing Constraints for the major IP components.
  • The Arm® CoreLink™ SSE-200 Subsystem for Embedded Technical Reference Manual.
  • The CoreLink™ SSE-200 Subsystem for Embedded Configuration and Integration Manual. This document assists with the implementation, integration, and interfacing of the SSE-200 into a larger System-on-Chip (SoC).
  • Verification reports.
  • System level IP-XACT descriptions.
  • UPF 2.0 power intent description.
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