2.6 System control element

The System control element provides the following features:

  • AHB5 to APB protocol conversion with a Peripheral Protection Unit.

    See the Arm® CoreLink™ SIE-200 System IP for Embedded Technical Reference Manual.

  • System control registers:

    • SPIDEN, SPNIDEN controls, and overrides.
    • Syndrome (status) of last reset.
    • General-purpose retention register for general use.
  • Reset generation.
  • Always-on components that run on the slow clock (for example 32KHz):
    • Watchdog reset and interrupt generation.
    • Timer.
  • Power control:
    • Power Dependency Control Matrix (PDCM) generates external wakeup for elements with PPU and for expansion power domains.
    • Access to Power Policy Units (PPUs) within Power Integration Kits (PIKs).

      Note:

      Power control is customizable by the customer to integrate control and communication with SSE-200 components and components outside the SSE-200 Subsystem. See also 2.8 Power control infrastructure.
  • Clock generation and control:

    • Clock divider and multiplexing settings.
    • Clock and reset override controls.
    • External Wakeup Interrupt Control to capture interrupts and wake up the MAINCLK and processors in hibernation on interrupt.
    • Generation of FCLK and SYSCLK from MAINCLK with clock dividers.
    • Dynamic hierarchical clock gating for PPU clocks.
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