2.2 Top-level system partitioning

The SSE-200 components are organized into the following blocks or elements:

  • Base element.
  • CPU elements.
  • Debug element.
  • System control element.
  • SRAM elements.
  • Crypto element.

The top-level view of the SSE-200 Subsystem elements and the AHB5 and APB bus interconnections is shown in the following figure. The following abbreviations are used in the figure:

ACGAHB5/APB Access Control Gate.
EAMAHB5 Exclusive Access Monitor.
MHUMessage Handling Unit.
MPCAHB5 Memory Protection Controller.
MSCMaster Security Controller.
PCSMPower Control State Machine.
PIKPower Integration Kit.
PPCAHB5/APB Peripheral Protection Controller.
Figure 2-1 Top-level element interconnections
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