2.3 CPU elements

There are two Cortex®-M33 cores in the SSE-200:

  • The primary core in the CPU0 element is synchronous to main interconnect and runs the operating system.
  • The secondary core in the CPU1 element typically contains an FPU and/or DSP. It is synchronous to the main clock, but could run N times faster.

The Cortex-M33 processor has the following features:

  • Three-stage pipeline.
  • Arm®v8-M Mainline profile.
  • TrustZone®-M security.
  • Up to eight SAU entries each (configurable).
  • Up to 16 MPU regions with eight Secure and eight Non-secure (configurable).
  • IDAU defining high-level security memory mapping.

Each processor has configuration parameters that can be set in the design stage to specify the processor features including:

  • If the FPU is present.
  • If the Digital Signal Processing extension instructions are included.
  • The number of Non-secure and Secure MPU regions.
  • The number of security attribution unit regions.
  • The number of user interrupts.
  • The interrupt priority and interrupt latency that is implemented in the NVIC.
  • Debug resources and trace support.
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