2.4 Base element

The Base element provides the following features:

  • A multilayer AHB5 interconnect for all the subsystem elements and expansion buses.

  • A Memory Protection Controller for each SRAM element.

  • AHB to APB bus converters and TrustZone® Peripheral Protection Controllers for:

    • Two CMSDK Timers.

    • One CMSDK Dual Timer.
    • One CMSDK Watchdog timers.
    • Message Handling Units that can send messaging interrupts to each core.
  • Two AHB5 slave expansion ports and three master expansion ports.
  • A security controller with expansion support.
  • A single voltage domain and power-gated region.
  • Two synchronous clock domains.
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