3.3 Control and Status Register Map for sdc600_comap

This variant can be used with ADIv5.2 debug subsystems, such as Arm® CoreSight™ SoC-400 implementations.

The following figure shows the register map.

Figure 3-2 Control and Status Register map for ADIv5.2 debug subsystems
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The following table shows the registers offset from the base memory address.

Table 3-2 Control and Status Register table for ADIv5.2 debug subsystems

Offset Description
0xFC 3.3.1 Identification Register
0xF8-0x40 Reserved
0x3C-0x00 SDC-600 Control and Status Registers
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