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This document gives reference information for the SDC-600 Secure Debug Channel.
n identifier indicates the revision status of the product described in this book, for example, r
|r||Identifies the major revision of the product, for example, r1.|
|p||Identifies the minor revision or modification status of the product, for example, p2.|
This book is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the Arm® SDC-600 Secure Debug Channel product.
This book is organized into the following chapters:
This chapter provides an overview of the Arm® CoreSight™ SDC-600 Secure Debug Channel.
This chapter describes the functionality of the SDC-600.
This chapter provides a description of the address map and registers of the SDC-600.
This chapter describes the signals of the SDC-600.
This appendix describes the technical changes between released issues of this book.
The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.
See the Arm® Glossary for more information.
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.
The signal conventions are:
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:
HIGH for active-HIGH signals.
LOW for active-LOW signals.
At the start or end of a signal name denotes an active-LOW signal.
This book contains information that is specific to this product. See the following documents for other relevant information.