3.2 Control and Status Register Map for sdc600_apbcom_ext

This variant can be used with ADIv6 debug subsystems, such as Arm® CoreSight™ SoC-600 implementations.

The following figure shows the register map.

Figure 3-1 Control and Status Register map for ADIv6 debug subsystems
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The following table shows the registers offset from the base memory address.

Table 3-1 Control and Status Register table for ADIv6 debug subsystems

Offset Description
0xFFC-0xEFC CoreSight Management Registers
0xEF8-0xD40 Reserved
0xD3C-0xD00 SDC-600 Control and Status Registers
0xCFC-0x000 Reserved
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