3.2 Control and Status Register Map for sdc600_apbcom_ext

This variant can be used with ADIv6 debug subsystems, such as Arm® CoreSight™ SoC-600 implementations.

The following figure shows the register map.

Figure 3-1 Control and Status Register map for ADIv6 debug subsystems
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the registers offset from the base memory address.

Table 3-1 Control and Status Register table for ADIv6 debug subsystems

Offset Description
0xFFC-0xEFC CoreSight Management Registers
0xEF8-0xD40 Reserved
0xD3C-0xD00 SDC-600 Control and Status Registers
0xCFC-0x000 Reserved
Non-ConfidentialPDF file icon PDF version101130_0002_02_en
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.