3.6.7 Data Blocking Register
This register is used to send data via the TxEngine and receive data from the RxEngine.
The DBR characteristics are:
- Usage constraints
- Upper bytes must be the NULL flag (
0xAF) on writes.
- Available in all SDC-600
- 32-bit read/write memory-mapped register located at offset
The DR and DBR operate identically, except on writes where more data is written to the TxEngine than the COM Port can accept. In this case:
- When writing to the DR, the write access completes with an OK
response and an overflow error is logged in SR.TXOE.
- When writing to the DBR, the write access stalls until there is
The following figure shows the bit assignments.
3-12 DBR bit assignments
The following table shows the bit assignments.
3-13 DBR bit assignments
Data transfer. Only 32-bit access size is supported to DBR.
- Transfers the lowest byte into the TxEngine
FIFO for transmission.
- The upper bytes must be written with the
NULL Flag byte value.
- The TxEngine ignores the NULL Flag byte
- If TxEngine FIFO is not empty and the byte
to be transmitted to the TxEngine is not a NULL Flag byte,
the write to the DBR stalls until the FIFO empties.
- If SR.TXOE or SR.TXLE is 1, then writes are
- If SR.TXLE is 1, then writes are ignored
and any outstanding write access is terminated with an OK
- Returns one byte from the RxEngine FIFO at
the lowest byte.
- If the RxEngine FIFO is empty, the lowest
byte returns the NULL Flag byte. The upper bytes always
return the NULL Flag byte.
- Read accesses complete immediately.