A.6 Debug Splitter signals

The following tables show the signals of the Debug Splitter component.

Table A-53 Debug Splitter system signals

Name Direction Description
CLK Input The bus clock times all bus transfers. All signal timings are related to the rising edge.
RESET_N Input Active-LOW reset signal that resets the system and the bus.

Note:

The SLV prefix in the following signals is specific to the Cortex-M Debug protocol. The _S and _M endings of the signal name indicate whether the signal belongs to the Slave or Master interface.

Table A-54 Debug Splitter Cortex-M Debug slave interface signals

Name Direction Description
SLVADDR_S[31:0] Input The 32-bit wide address bus.
SLVPROT_S[6:0] Input

The protection control signals provide additional information about a bus access and are primarily intended for use by any module that wants to implement some level of protection.

The signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a privileged-mode access or user-mode access. For masters with a Memory Management Unit, these signals also indicate whether the current access is cacheable or bufferable.

SLVNONSEC_S Input Indicates if the current transfer is a Non-secure transfer or a Secure transfer.
SLVTRANS_S[1:0] Input Indicates the transfer type of the current transfer. IDLE or NONSEQUENTIAL.
SLVWDATA_S[31:0] Input The write data bus transfers data from the master to the slaves during write operations. The data bus width is fixed at 32 bits.
SLVWRITE_S Input Indicates the transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer. It has the same timing as the address signals.
SLVREADY_S Output When HIGH, the HREADY signal indicates to the master that the previous transfer is complete.
SLVRDATA_S[31:0] Output During read operations, the read data bus transfers data from the selected slave to the multiplexer. The multiplexer then transfers the data to the master. The data bus width is fixed at 32 bits.
SLVRESP_S Output The transfer response provides the master with additional information on the status of a transfer. LOW means OKAY and HIGH means ERROR.

Table A-55 Debug Splitter Cortex-M Debug master interface signals

Name Direction Description
SLVADDR_M[31:0] Output The 32-bit wide address bus.
SLVPROT_M[6:0] Output

The protection control signals provide additional information about a bus access and are primarily intended for use by any module that wants to implement some level of protection.

The signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a privileged-mode access or user-mode access. For masters with a Memory Management Unit, these signals also indicate whether the current access is cacheable or bufferable.

SLVSIZE_M[1:0] Output Indicates the size of the transfer, which is byte, halfword, or word.
SLVNONSEC_M Output Indicates if the current transfer is a Non-secure transfer or a Secure transfer.
SLVTRANS_M[1:0] Output Indicates the transfer type of the current transfer. IDLE or NONSEQUENTIAL.
SLVWDATA_M[31:0] Output The write data bus transfers data from the master to the slaves during write operations. The data bus width is fixed at 32 bits.
SLVWRITE_M Output Indicates the transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer. It has the same timing as the address signals.
SLVREADY_M Input When HIGH, the HREADY signal indicates to the master that the previous transfer is complete.
SLVRDATA_M[31:0] Input During read operations, the read data bus transfers data from the selected slave to the multiplexer. The multiplexer then transfers the data to the master. The data bus width is fixed at 32 bits.
SLVRESP_M Input The transfer response provides the master with additional information on the status of a transfer. LOW means OKAY and HIGH means ERROR.

Table A-56 Debug Splitter APB4 master interface signals

Name Direction Description
PADDR_M[11:0] Output The APB address bus, which is driven by the peripheral bus bridge unit.
PSEL_M Output Indicates that the APB slave device is selected and that a data transfer is required.
PENABLE_M Output Indicates the second and subsequent cycles of an APB transfer.
PWRITE_M Output Indicates an APB Write-Access when HIGH and an APB read access when LOW.
PWDATA_M[31:0] Output This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE_M is HIGH.
PRDATA_M[31:0] Input The selected APB slave drives this bus during read cycles when PWRITE_M is LOW.
PREADY_M Input The APB slave uses this signal to extend an APB transfer.
PSLVERR_M Input

This signal indicates a transfer failure.

Note:

Tie this input LOW when connecting to an APB slave device that does not provide a PSLVERR output, such as apbcom_ext_rom.

Table A-57 Authentication interface signals

Name Direction Description
SPNIDEN Input Secure non-invasive debug enable.
SPIDEN Input Secure invasive debug enable.
NIDEN Input Non-secure non-invasive debug enable.
DBGEN Input Non-secure invasive debug enable.

See the Authentication Interface section of the ARM CoreSight Architecture Specification v3.0 for more information about the authentication interface signals.

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