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This section describes the interface to the External components for each variant.
For ADIv6-compliant systems, the APB interface connects the External APBCOM to the Debug Port (DP) through APB infrastructure components. It is preferable for the External APBCOM to be high in the APB infrastructure hierarchy.
The External APBCOM also has a DP_ABORT signal. An abort request causes the External APBCOM to terminate the current transaction. Abort requests only affect APB write transactions to the Data Blocking Register (DBR) stalled by a transaction still in progress on the CWI Tx interface. Other transactions, which are guaranteed to complete in a finite amount of time, ignore the abort and are allowed to complete normally.
When an abort occurs:
For ADIv5.2-compliant systems, the DAPBUS interface connects the COM-AP to the Debug Port (DP) through the DAPBUS Interconnect (DAPIC).
The COM-AP has the DAPABORT signal, which is part of the DAPBUS interface and has the same functionality as the DP_ABORT with APB.
See 3.3 Control and Status Register Map for sdc600_comap for address map configuration.
For Integrated Cortex-M DAP-compliant systems, the APBCOM for Integrated Cortex-M DAP is connected to the Integrated Cortex-M DAP module through the Debug Splitter. DP_ABORT is not implemented in Integrated Cortex-M DAP systems.
See 3.4 Control and Status Register Map for sdc600_apbcom_ext_rom for address map configuration.