3.6.2 Feature ID TxEngine Register

This register provides information about the features implemented in the COM Port TxEngine.

The FIDTXR characteristics are:

Usage constraints
There are no usage constraints.
Configurations
Available in all SDC-600 configurations.
Attributes
32-bit read-only memory-mapped register located at offset 0x08.

The following figure shows the bit assignments.

Figure 3-7 FIDTXR bit assignments
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The following table shows the bit assignments.

Table 3-8 FIDTXR bit assignments

Bits Name Function
[31:20] - res0.
[19:16] TXFD TxEngine FIFO depth. The defined value of this field is:
0x0

TxEngine FIFO has a capacity of 1 byte.

[15:11] - res0.
[10] TXSZ32 TxEngine 32-bit write support. The defined value of this bit is:
0x1

TxEngine supports 32-bit wide writes.

[9] TXSZ16 TxEngine 16-bit write support. The defined value of this bit is:
0x0

TxEngine does not support 16-bit wide writes.

[8] TXSZ8 TxEngine 8-bit write support. The defined value of this bit is:
0x0

TxEngine does not support 8-bit wide writes.

[7:4] TXW TxEngine Width. Indicates the implemented width of the TxEngine. The defined value of this field is:
0x11-byte wide TxEngine. The upper bytes must be the NULL flag (0xAF). For example, to write 0x12 to the TxEngine, the APB write data is 0xAFAFAF12.
[3:2] - res0.
[1] TXINT Indicates whether the TxEngine generates interrupts. The defined values of this bit are:
0x0

TxEngine interrupts not implemented.

0x1

TxEngine interrupts implemented.

Note:

Only sdc600_apbcom_int has interrupt capabilities. The external COM Port modules do not have interrupt functionality.

If the TxEngine interrupts are implemented, the following are implemented:

  • ICSR.TXFIL
  • ICSR.TXFIS
[0] TXI Indicates whether the TxEngine is implemented. The defined value of this bit is:
0x1

TxEngine implemented.

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