3.6.3 Feature ID RxEngine Register

This register provides information about the features implemented in the COM Port RxEngine.

The FIDRXR characteristics are:

Usage constraints
There are no usage constraints.
Configurations
Available in all SDC-600 configurations.
Attributes
32-bit read-only memory-mapped register located at offset 0x0C.

The following figure shows the bit assignments.

Figure 3-8 FIDRXR bit assignments
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The following table shows the bit assignments.

Table 3-9 FIDRXR bit assignments

Bits Name Function
[31:20] - res0.
[19:16] RXFD RxEngine FIFO depth. The defined value of this field is:
0x0

RxEngine FIFO has a capacity of 1 byte.

[15:11] - res0.
[10] RXSZ32 RxEngine 32-bit read support. The defined value of this bit is:
0x1

RxEngine supports 32-bit wide reads.

[9] RXSZ16 RxEngine 16-bit read support. The defined value of this bit is:
0x0

RxEngine does not support 16-bit wide reads.

[8] RXSZ8 RxEngine 8-bit read support. The defined value of this bit is:
0x0

RxEngine does not support 8-bit wide reads.

[7:2] - res0.
[1] RXINT Indicates whether the RxEngine generates interrupts. The defined values of this bit are:
0x0

RxEngine interrupts not implemented.

0x1

RxEngine interrupts implemented.

Note:

Only sdc600_apbcom_int has interrupt capabilities. The external COM Port modules do not have interrupt functionality.

If the RxEngine interrupts are implemented, the following are implemented:

  • ICSR.RXFIL
  • ICSR.RXFIS
[0] RXI Indicates whether the RxEngine is implemented. The defined value of this bit is:
0x1

RxEngine implemented.

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