A.2 Signals for the sdc600_comap

The following tables show the signals of the ADIv5.2 COM-AP component.

Table A-8 COM-AP, system signals

Name Direction Description
DAPCLK Input The main clock. All signal timings are related to the rising edge.
DAPRESET_N Input Active-LOW reset signal.

Remote reboot request disable signal from the application that drives the read-only SR.RRDIS bit of the external COM Port components.

It provides control to an application or the lifecycle state management of the chip to prevent rebooting the target system through the SDC-600 when it is no longer needed.

CDC synchronizer flops are implemented inside the module for this input, so changing the value of this signal during operation is allowed.

If this feature is not required, Arm recommends that you disable it so that this feature is not exposed to the debugger.


COM Port enable that drives the read-only SR.PEN bit of the External COM Port components.

If not set:

  • Writes to DR and DBR are ignored.
  • Reads of DR and DBR behave as if the RxEngine FIFO would be empty.

It is expected to be a static configuration, therefore no CDC synchronizer flops are implemented inside the module for this input.

Table A-9 COM-AP, DAPBUS signals

Name Direction Description
DAPCADDR_S [7:0] Input Compressed address bus from the DP.
DAPWRITE_S Input Indicates the direction of the data transfer. When HIGH, write is enabled. When LOW, read is enabled.
DAPSEL_S Input When HIGH, the DAP Bus slave is selected.
DAPENABLE_S Input Starts the DAP Bus transfer when DAPWRITE_S is HIGH.
DAPWDATA_S [31:0] Input The data input of the DAP Bus slave when DAPWRITE_S is HIGH.
DAPRDATA_S [31:0] Output The selected slave drives this bus when DAPWRITE_S is LOW.
DAPREADY_S Output The COM-AP uses this ready signal to extend the transfer. Its inactive state is LOW.
DAPSLVERR_S Output The COM-AP uses this error signal to indicate that an error occurred during the transfer and the transfer was aborted.
DAPABORT_S Input When a transfer takes more time than expected, the DAP is able to abort the transfer. When HIGH, the transfer either finishes normally in deterministic short time or is aborted.

Table A-10 COM-AP, CWI-RX signals

Name Direction Description
RX_VALID Input Data valid.
RX_READY Output Data ready. Indicates the completion of a transfer.
RX_DATA[7:0] Input Data line from the Internal APBCOM’s TxEngine.
RX_LINKEST Input Link established signal from Internal APBCOM.
RX_LINKUP Output Linkup indicated to Internal APBCOM.

Table A-11 COM-AP, CWI-TX signals

Name Direction Description
TX_VALID Output Data valid.
TX_READY Input Data ready. Indicates the completion of a transfer.
TX_DATA[7:0] Output Data line to Internal APBCOM’s RxEngine.
TX_LINKEST Output Link established signal to Internal APBCOM.
TX_LINKUP Input Linkup indicated from Internal APBCOM.

Table A-12 COM-AP, Powerup Request signals

Name Direction Description
REMPUR Output Remote powerup request to the power control unit.
REMPUA Input Remote powerup acknowledge from the power control unit.
REMRR Output Remote reboot request to the power control unit.
REMRA Input Remote reboot acknowledge from the power control unit.

Table A-13 COM-AP, Q-Channel for clock signals

Name Direction Description
CLK_QREQ_N Input Asynchronous quiescence request signal for the clock.
CLK_QACCEPT_N Output When LOW, the quiescent request is accepted for the clock.
CLK_QDENY Output When HIGH, the quiescent request is denied for the clock.
CLK_QACTIVE Output When HIGH, indicates to the controller that the component requires the clock.
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