The SDC-600 Secure Debug Channel can be integrated into various systems, and the components that are used vary depending on the system.
The SDC-600 contains the following components:
- An External component, which is used on the debugger side and recognized as a special access port (COM-AP) or a CoreSight™ peripheral device (APBCOM) by the debugger. The External component has three different variants depending on the debug infrastructure version:
- The External APBCOM, which is used in ADIv6-compliant systems.
- The External APBCOM for Integrated Cortex-M DAP, which is used with processor cores with Integrated Cortex-M DAP. This component is a CoreSight ROM table that includes COM functionality.
- The COM-AP, which is used in ADIv5.2-compliant systems.
- An Internal component, which is the Internal APBCOM. The Internal component is accessible by the target processor core through the system interconnect.
- A COM asynchronous bridge, which transfers data between different clock and power domains. The asynchronous bridge has two variants:
- An area-optimized bridge (Direct Bridge), which can be used in systems where the internal and external components are in neighboring power and clock domains.
- A traditional bridge (Indirect Bridge), which can be used in any system, and can be instantiated multiple times on a CWI channel if passing multiple domains.
- A Debug Splitter, which is a module that is placed between the SLV master interface of the Integrated Cortex-M DAP and the SLV slave port of the processor core in non-AHB-Lite compliant mode. The Debug Splitter is only required with systems using the Integrated Cortex-M DAP of the processor core. The Debug Splitter supports the following Arm® Cortex® processor cores:
- Arm Cortex-M0.
- Arm Cortex-M0+.
- Arm Cortex-M7.
- Arm Cortex-M23.
- Arm Cortex-M33.