1.6 Design Process

The SDC-600 components are delivered as synthesizable Verilog RTL. Before the SDC-600 components can be used in a product, they must go through the following processes:

System design
Determining the necessary structure and interconnections of the SDC-600 components that form the CoreSight™ secure debug channel.
Defining the memory map of the system and the functional configuration of the SDC-600 components.
Connecting the SDC-600 components together, and to the SoC memory and debug systems.
Verifying that the CoreSight secure debug channel has been correctly integrated to the processor or processors in your SoC.
Using the Verilog RTL in an implementation flow to produce a hard macrocell.

The operation of the final device depends on:

The implementer chooses the options that affect how the RTL source files are pre-processed. These options usually include, or exclude, logic that affects one or more of the area, maximum frequency, and features of the resulting macrocell.
Software configuration
The programmer configures the CoreSight secure debug channel by programming specific values into registers that affect the behavior of the SDC-600 components.
This section contains the following subsection:
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