A.4 Signals for the sdc600_apbcom_int

This section describes the signals used with the internal APBCOM.

Table A-21 Internal APBCOM system signals

Name Direction Description
PCLK Input The main clock. All signal timings are related to the rising edge.
PRESET_N Input Active-LOW reset signal.

Table A-22 Internal APBCOM APB4 signals

Name Direction Description
PADDR_S[11:0] Input Address bus.
PWRITE_S Input Indicates the direction of the data transfer. When HIGH, write is enabled. When LOW, read is enabled.
PSEL_S Input When HIGH, the APB slave is selected.
PENABLE_S Input Starts the APB transfer one cycle after PSEL.
PWDATA_S [31:0] Input The data input of the APB slave when PWRITE_S is HIGH.
PRDATA_S [31:0] Output The selected slave drives this bus when PWRITE_S is LOW.
PREADY_S Output The Internal APBCOM uses this ready signal to extend the transfer if it is in low-power state during the transfer initiation. Its inactive state is LOW.

Table A-23 Internal APBCOM CWI-RX signals

Name Direction Description
RX_VALID Input Data valid.
RX_READY Output Data ready. Indicates the completion of a transfer.
RX_DATA[7:0] Input Data line from the External component's TxEngine.
RX_LINKEST Input Link established signal from the External component.
RX_LINKUP Output Linkup indicated to the External component. The reset value is LOW.

Table A-24 Internal APBCOM CWI-TX signals

Name Direction Description
TX_VALID Output Data valid.
TX_READY Input Data ready. Indicates the completion of a transfer.
TX_DATA[7:0] Output Data line to the External component's RxEngine. The reset value is LOW.
TX_LINKEST Output Link established signal to the External component. The reset value is LOW.
TX_LINKUP Input Linkup indicated from the External component.

Table A-25 Internal APBCOM Q-Channel for clock and power signals

Name Direction Description
PWR_QREQ_N Input Asynchronous quiescence request signal for power.
PWR_QACCEPT_N Output When LOW, the quiescent request is accepted for the power.
PWR_QDENY Output When HIGH, the quiescent request is denied for the power.
PWR_QACTIVE Output When HIGH, indicates to the Q-Channel interface that the component requires power.
CLK_QREQ_N Input Asynchronous quiescence request signal for the clock.
CLK_QACCEPT_N Output When LOW, the quiescent request is accepted for the clock.
CLK_QDENY Output When HIGH, the quiescent request is denied for the clock.
CLK_QACTIVE Output When HIGH, indicates to the Q-Channel interface that the component requires the clock.

Table A-26 Internal APBCOM miscellaneous signals

Name Direction Description
IRQ Output Interrupt signal to the servicing agent. The reset value is LOW.
PWAKEUP_S Input Wake up request. Indicates that a new transaction is placed or about to be placed on the APB slave interface. This signal is assumed to stay asserted for the entire length of PSEL_S. It is guaranteed by the APB master to be glitch-free, and is used to drive CLK_QACTIVE.
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