2.3.6 Debug Splitter

The Debug Splitter is a module that is placed between the AHB master port of the Integrated Cortex-M DAP and the SLV (debug) port of the processor core in non-AHB-Lite compliant mode.

Note:

  • The Debug Splitter is not used in extendable ADIv6- or ADIv5.2-compliant debug subsystems.
  • The Debug Splitter can only be used with processor cores with Integrated Cortex-M DAP and can only be placed between the AHB master port of the Integrated Cortex-M DAP and the SLV (debug) port of the processor core.

The Debug Splitter module provides:

  • Access control on the Cortex-M debug interface.
  • Additional master interfaces to add another slave next to the processor core's debug port.
  • A Cortex®-M Debug slave interface for the Debug Access Port of the Integrated Cortex-M DAP on its debugger side.

On its target system side, it has:

  • A Cortex-M Debug master interface.
  • An APB4 master interface to the SDC-600.
  • An authentication input interface, through which the target system can enable the intercepted Cortex-M Debug master interface.

The Debug Splitter contains the following components:

  • A slave multiplexer.
  • A default slave.
  • A synchronous interface bridge.

The following figure shows the functional blocks of the Debug Splitter.

Figure 2-10 Debug Splitter block diagram
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Slave multiplexer

The slave multiplexer has three ports:

  • One for the path towards the processor core.
  • One for SDC-600 through the synchronous interface bridge.
  • One for the default slave.

Note:

  • If debug is not enabled, transactions are forwarded towards the default slave instead of the processor core, which terminates in an error. The path is therefore blocked by the address decoder when the debug is not enabled on the Authentication interface signals.
  • The multiplexer forwards all non-32-bit accesses that are addressed to the SDC-600 to the default slave.

Default slave

The default slave has a slave interface where only a few signals are taking part in the error response generation method.

The default slave conforms to default slave behavior as described in ARM® AMBA® 5 AHB Protocol Specification.

Synchronous interface bridge

The synchronous interface bridge connects a low-bandwidth APB4 peripheral device to the Cortex®-M Debug slave interface.

The synchronous interface bridge has the following interfaces:

  • A slave initiator interface to connect to the Cortex-M Debug master interface.
  • An APB4 master interface to connect to the sdc600_apbcom_ext_rom.

Note:

The clocks are common.
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