3.6.6 Status Register

This register indicates the current status of the COM Port component.

The SR characteristics are:

Usage constraints
There are no usage constraints.
Configurations
Available in all SDC-600 configurations.
Attributes
32-bit read/write memory-mapped register located at:
  • Offset 0x2C
  • Offset 0x3C
SR is aliased in more than one location. Accesses to any SR location access a single physical SR.

The following figure shows the bit assignments.

Figure 3-11 SR bit assignments
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The following table shows the bit assignments.

Table 3-12 SR bit assignments

Bits Name Function
[31] PEN COM Port component enabled status. The defined values of this bit are:
0x0

Component is disabled.

  • Writes to DR and DBR are ignored.
  • Reads of DR and DBR behave as if the RxEngine FIFO is empty.
0x1

Component is enabled.

This bit is read-only.

Reading this bit returns the value of the CFG_PEN input on the External components and 0x1 on the Internal APBCOM.

[30] RXLE RxEngine link error detected.

This bit is res0 because no link error can occur in the SDC-600 RxEngine.

[29:24] - res0.
[23:16] RXF RxEngine FIFO fill level. The possible values of this field are:
0x00

RxEngine has no data.

0x01

RxEngine has at least 1 byte available to read.

This field is read-only.

This field resets to 0x00.
[15] TRINPROG Transfer in progress. This bit is set when a transaction is aborted via DP_ABORT. The possible values of this bit are:
0x0

No transaction in progress.

0x1

An input transaction has been aborted but the internal operation of that transaction, or a previous transaction, is still in progress.

This bit is res0 in the External APBCOM for Integrated Cortex-M DAP and the Internal APBCOM components.

This bit resets to 0x0.
[14] TXLE TxEngine link error detected. The possible values of this bit are:
0x0

No link error detected.

0x1

A link error has been detected in the TxEngine.

This bit is set to 1 if:

  • The link is lost during a data transfer because the remote Rx interface module is not operating. A LERR flag byte is inserted into the local Rx FIFO.
  • One or more bytes written to the Tx FIFO are discarded because the link to the remote Rx interface module is not operating. A LERR flag byte is inserted into the local Rx FIFO.

This bit is read/write-one-to-clear.

This bit resets to 0x0.

[13] TXOE TxEngine FIFO overflow. The possible values of this bit are:
0x0

No overflow logged.

0x1

At least one byte written to TxEngine could not be accepted and has been lost.

This bit is read/write-one-to-clear.

This bit resets to 0x0.
[12] RRDIS Remote reboot requests disabled. The defined values of this bit are:
0x0

Remote Reboot requests enabled.

0x1

Remote Reboot requests disabled.

When this bit is 1, the TxEngine discards any LPH2RR Flag bytes written to the TxEngine.

This bit is read-only.

Reading this bit returns the value of the CFG_RRDIS input after synchronization in the External components and 0x1 in the Internal APBCOM.

[11:8] - res0.
[7:0] TXS TxEngine FIFO space. The defined values of this field are:
0x00

TxEngine has no space for new data.

0b1

TxEngine has at least 1 byte available.

This field resets to 0x01.

This field is read-only.

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