3.7 CoreSight™ Management Registers

Here are the CoreSight™ Management registers.

These registers are the same for each variant with the following exceptions:

  • The COM-AP component does not implement CoreSight Management Registers.
  • DEVID is only present in the Integrated Cortex-M DAP variant.
  • ITCTRL and ITSTATUS are RAZ/WI in the Internal and Integrated Cortex-M DAP variants.
  • CLAIMSET and CLAIMCLR are RAZ/WI in the Integrated Cortex-M DAP variant.
  • AUTHSTATUS is RAZ/WI in variants other than Integrated Cortex-M DAP variant.

Note:

For more information about these registers, see ARM® CoreSight™ Architecture Specification v3.0.

Table 3-14 CoreSight Management registers

Offset Type Size Register Reset Description
0xEFC RO 32 ITSTATUS 0 3.7.1 Integration Mode Status Register
0xF00 RW 32 ITCTRL 0 3.7.2 Integration Mode Control Register
0xFA0

RW

ROa

32 CLAIMSET

0x3

0a

Claim Tag Set Register
0xFA4

RW

ROa

32 CLAIMCLR 0 Claim Tag Clear Register
0xFA8 RO 32 DEVAFF0 0 Device Affinity Registers
0xFAC RO 32 DEVAFF1 0
0xFB0 RO 32 LAR 0 Software Lock Access Register
0xFB4 RO 32 LSR 0 Software Lock Status Register
0xFB8 RO 32 AUTHSTATUS

0

0xAAa

Authentication Status Register
0xFBC RO 32 DEVARCH 0x4770_0A57 Device Architecture Register: CoreSight SDC-600
0x4770_0AF7 Device Architecture Register: CoreSight ROM Table
0xFC0 RO 32 DEVID2 0 Device Configuration Register 2
0xFC4 RO 32 DEVID1 0 Device Configuration Register 1
0xFC8 RO 32 DEVID

0x00

0x40a

3.7.3 Device ID Register
0xFCC RO 32 DEVTYPE 0 Device Type Identifier Register
0xFD0 RO 32 PIDR4 0x04b Peripheral ID Register
0xFD4 RO 32 PIDR5 0 Peripheral ID Register
0xFD8 RO 32 PIDR6 0 Peripheral ID Register
0xFDC RO 32 PIDR7 0 Peripheral ID Register
0xFE0 RO 32 PIDR0 0xB9b Peripheral ID Register
0xFE4 RO 32 PIDR1 0xEFb Peripheral ID Register
0xFE8 RO 32 PIDR2 0x0Bb Peripheral ID Register
0xFEC RO 32 PIDR3 0x00b Peripheral ID Register
0xFF0 RO 32 CIDR0 0x0D Component ID Register
0xFF4 RO 32 CIDR1 0x90 Component ID Register
0xFF8 RO 32 CIDR2 0x05 Component ID Register
0xFFC RO 32 CIDR3 0xB1 Component ID Register
This section contains the following subsections:
a 

This value is only for sdc600_apbcom_ext_rom.

b 

The reset value for sdc600_apbcom_ext_rom is parameter dependant.

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