3.6.5 Data Register

This register is used to send data via the TxEngine and receive data from the RxEngine.

The DR characteristics are:

Usage constraints
Upper bytes must be the NULL flag (0xAF) on writes.
Available in all SDC-600 configurations.
32-bit read/write memory-mapped register located at offset 0x20.

The DR and DBR operate identically, except on writes where more data is written to the TxEngine than the COM Port can accept. In this case:

  • When writing to the DR, the write access completes with an OK response and an overflow error is logged in SR.TXOE.
  • When writing to the DBR, the write access stalls until there is sufficient space.

This register is RW.

This register resets to 0xAFAFAFAF.

The following figure shows the bit assignments.

Figure 3-10 DR bit assignments
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The following table shows the bit assignments.

Table 3-11 DR bit assignments

Bits Name Function
[31:0] DATA

Data transfer. Only 32-bit accesses are supported to DR.

On writes:

  • Transfers the lowest byte into the TxEngine FIFO for transmission.
  • The upper bytes must be written with the NULL Flag byte value.
  • The TxEngine ignores the NULL Flag byte value.
  • If TxEngine FIFO is not empty and the byte to be transmitted to the TxEngine is not a NULL Flag byte, a TxEngine Overflow error occurs and SR.TXOE is set to 1. The byte is discarded by the TxEngine.
  • If SR.TXOE or SR.TXLE is 1, then writes are ignored.
  • Write accesses complete immediately.

On reads:

  • Returns one byte from the RxEngine FIFO at the lowest byte.
  • If the RxEngine FIFO is empty, the lowest byte returns the NULL Flag byte. The upper bytes always return the NULL Flag byte value of 0xAF.
  • Read accesses complete immediately.
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