A.5.3 External direct half bridge signals

The following tables show the signals for the external direct half bridge.

Table A-41 External direct half bridge system signals

Name Direction Description
CLK_EXT Input Clock for the external side of the bridge. All signal timings are related to the rising edge.
RESETN_EXT Input Active-LOW reset for CLK_EXT domain.

Table A-42 External direct half bridge COM-RX signals

Name Direction Description
EXT_RX_DATA[7:0] Input Receive data from External component.
EXT_RX_VALID Input Data valid.
EXT_RX_READY Output Data accepted, ready delivered by bridge.
EXT_RX_LINKUP Output Linkup indicated by the Internal APBCOM to the External component.
EXT_RX_LINKEST Input Link established from the External component to the Internal APBCOM.

Table A-43 External direct half bridge COM-TX signals

Name Direction Description
EXT_TX_DATA[7:0] Output Data transmitted to the External component.
EXT_TX_VALID Output Data valid.
EXT_TX_READY Input Data accepted.
EXT_TX_LINKUP Input Linkup indicated by the External component to the Internal APBCOM.
EXT_TX_LINKEST Output Link established from the Internal APBCOM to the External component.

Table A-44 External direct half bridge asynchronous COM External to Internal signals

Name Direction Description
EXT_ASYNC_EI_REQ Output Transmit request handshake signal.
EXT_ASYNC_EI_ACK Input Transmit acknowledge handshake signal.
EXT_ASYNC_EI_DATA[7:0] Output Transmit data.
EXT_ASYNC_EI_LINKEST Output Link established from the External component to the Internal APBCOM.
EXT_ASYNC_EI_LINKUP Input Linkup indicated by the Internal APBCOM to the External component.

Table A-45 External direct half bridge asynchronous COM Internal to External signals

Name Direction Description
EXT_ASYNC_IE_REQ Input Receive data available handshake signal.
EXT_ASYNC_IE_ACK Output Receive data captured handshake signal.
EXT_ASYNC_IE_DATA[7:0] Input Receive data.
EXT_ASYNC_IE_LINKEST Input Link established from the Internal APBCOM to the External component.
EXT_ASYNC_IE_LINKUP Output Linkup indicated by the External component to the Internal APBCOM.

Table A-46 External direct half bridge Clock Q-Channel signals

Name Direction Description
EXT_CLK_QREQ_N Input Asynchronous quiescence request signal for CLK_EXT.
EXT_CLK_QACCEPT_N Output When LOW, the quiescent request is accepted for CLK_EXT.
EXT_CLK_QDENY Output When HIGH, the quiescent request is denied for CLK_EXT.
EXT_CLK_QACTIVE Output When HIGH, indicates to the controller that the component requires the clock on CLK_EXT.
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