3.4 Control and Status Register Map for sdc600_apbcom_ext_rom

This variant can be used with systems with Integrated Cortex-M DAP.

The following figure shows the register map.

Figure 3-4 Control and Status Register map for systems with Integrated Cortex-M DAP
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The following table shows the registers offset from the base memory address.

Table 3-4 Control and Status Register table for systems with Integrated Cortex-M DAP

Offset Description
0xFFC-0xFB8 CoreSight Management Registers
0xFB4-0xD40 Reserved
0xD3C-0xD00 SDC-600 Control and Status Registers
0xCFC-0x004 Reserved
0x000 ROMENTRY0
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