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The Clock Controller (CLK-CTRL) provides high-level clock gating for devices in a clock domain that support Q-Channel Low Power Interface (LPI) clock gating. The CLK-CTRL uses the Q-Channels to ensure that the devices are in a quiescent state before it gates the clock. The CLK-CTRL also ensures that the clock is running, before it allows a device to exit the quiescent state.
The following figure shows the main interfaces on the CLK-CTRL.
The CLK-CTRL monitors the Q-Channel clk_qactive_i inputs, to know when it must perform the Q-Channel requests. When all the Q-Channels are in the quiescent state, the CLK-CTRL sets clken_o LOW, to stop the clock. When any clk_qactive_i goes HIGH, the CLK-CTRL enables the clock and moves all the device Q-Channels to the running state. You can apply 0-255 clk cycles of hysteresis to the quiescence entry, by altering the state of the entry_delay_i[7:0] configuration input.
You can disable the clock gating feature by setting clk_force_i HIGH.
The NUM_Q_CHL configuration parameter controls how many Q-Channel interfaces are on the CLK-CTRL.
The NUM_QACTIVE_ONLY configuration parameter controls how many QACTIVE-only interfaces are on the CLK-CTRL.
The CLK-CTRL has two optional hierarchical control Q-Channels. You can connect a higher-level clock or power controller to the following hierarchical Q-Channels:
See the Arm® Clock Controller Architecture Specification, version 1.0 for more information about the CLK-CTRL functionality.