A.6 PPU signals

The following tables show the Power Policy Unit signals.

The following table lists the clock and reset signals.

Table A-22 PPU clock and reset signals

Signal Type Clock Description
clk Input - Clock input.
reset_n Input clk An active-LOW reset input. reset_n can assert asynchronously, but must deassert synchronous to clk.

The following table lists the APB programming interface signals.

Table A-23 PPU programming interface signals

Signal Type Clock Description
psel_i Input clk See the Arm® AMBA® APB Protocol Specification Version 2.0 for information about these signals.
penable_i
paddr_i[31:0]
pwrite_i
pwdata_i[31:0]
pwakeup_i The PPU uses this wakeup signal as an input for the generation of the ppuclk_qactive_o signal. This signal must be driven from a register.
prdata_o[31:0] Output See the Arm® AMBA® APB Protocol Specification Version 2.0 for information about these signals.
pready_o
pslverr_o

The following table lists the clock Q-Channel signals.

Table A-24 PPU clock Q-Channel signals

Signal Type Clock Description
ppuclk_qreqn_i Input Either:
  • Asynchronous, when QCLK_SYNC_EN == 1.
  • clk, when QCLK_SYNC_EN == 0.
This signal indicates when the clock controller that controls the PPU clk input, issues a quiescence entry or exit request to the PPU.
ppuclk_qacceptn_o Output clk This signal indicates when the PPU accepts a quiescence request to gate its clock.
ppuclk_qdeny_o This signal indicates when the PPU denies a quiescence request to gate its clock.
ppuclk_qactive_o This signal indicates when the PPU requires the clk signal.

The following table lists the P-Channel signals.

Table A-25 PPU P-Channel signals

Signal Type Clock Description
dev_preq_o Output clk

This signal indicates when the PPU issues a power mode request to the PPU devices.

At reset, this signal is LOW.

dev_pstate_o[P_CH_PSTATE_LEN−1:0]

The PPU sends the power mode and operating mode that is requested, when dev_preq_o is set HIGH.

At reset, this signal is LOW.

dev_paccept_i Input Either:
  • Asynchronous, when DEV_ACTIVE_SYNC_EN == 1.
  • clk, when DEV_ACTIVE_SYNC_EN == 0.
This signal indicates when a PPU device accepts the power mode request.
dev_pdeny_i This signal indicates when a PPU device denies the power mode request.
dev_pactive_i[P_CH_PACTIVE_LEN−1:0] This signal indicates the power mode that the device requests.

The following table lists the Power Control State Machine (PCSM) P-Channel signals.

Table A-26 PPU PCSM P-Channel signals

Signal Type Clock Description
pcsm_preq_o Output clk

This signal indicates when the PPU issues a power mode request to the PCSM.

At reset, this signal is LOW.

pcsm_pstate_o[P_CH_PSTATE_LEN−1:0] The power mode and operating mode that the PPU requests, when pcsm_preq_o is set HIGH.
pcsm_paccept_i Input Either:
  • Asynchronous, when PCSM_SYNC_EN == 1.
  • clk, when PCSM_SYNC_EN == 0.
This signal indicates when the PCSM accepts the power mode request.
pcsm_mode_stat_i[P_CH_PSTATE_LEN−1:0] Input clk This signal provides the MODESTAT information from the PSCM.

The following table lists the device control signals. See the Arm® Power Policy Unit Architecture Specification, version 1.1 for more information.

Table A-27 PPU device control signals

Signal Type Clock Description
ppuhwstat_o[20:0] Output clk This signal indicates the current mode of the PPU.
devclken_o  

Device clock enable.

devemuclken_o  

Device emulated mode clock enable.

devisolaten_o   Device isolation control.
devemuisolaten_o   Device emulated isolation control.
devwarmresetn_o   The Warm reset for non-retention registers.
devretresetn_o   The Warm reset for retention registers.
devporesetn_o   Device reset.

The following table lists the interrupt and revision signals.

Table A-28 PPU interrupt and revision signals

Signal Type Clock Description
irq_o Output clk Interrupt signal.
ecorevnum_i Input Asynchronous A 4-bit signal that you can use to alter the value of the PPU_IIDR.REVISION and PID3.REVAND fields. See 3.3 Implementation Identification Register, PPU_IIDR and 3.4.8 Peripheral ID 3.

The following table lists the Design for Test (DFT) signals.

Table A-29 PPU DFT signals

Signal Type Clock Description
dftcgen Input Asynchronous This signal opens the architectural clock gates, and ensures that clk is active during shift mode.
dftisodisable Input Asynchronous Provides an override for the PPU isolation control signals. Use in DFT mode only.
dftrstdisable Input Asynchronous Provides an override for the PPU reset output signals. Use in DFT mode only.
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