A.1 LPD-Q Q-Channel Distributor signals

The following tables show the Low Power Distributor Q-Channel signals.

The following table lists the clock and reset signals.

Table A-1 LPD-Q clock and reset signals

Signal Type Clock Description
clk Input - Clock input.
reset_n Input clk An active-LOW reset input. reset_n can assert asynchronously, but must deassert synchronous to clk.
clk_qactive_o Output clk This signal indicates when the LPD-Q is active and it requires the clk signal.

The following table lists the control interface signals.

Table A-2 LPD-Q control interface signals

Signal Type Clock Description
ctrl_qreqn_i Input Either:
  • Asynchronous, when CTRL_Q_CH_SYNC == 1.
  • clk, when CTRL_Q_CH_SYNC == 0.
This signal indicates when the controller issues a quiescence entry or exit request to the LPD-Q.
ctrl_qacceptn_o Output clk This signal indicates when all the LPD-Q devices accept the quiescence request.
ctrl_qdeny_o This signal indicates when one or more LPD-Q devices deny the quiescence request.
ctrl_qactive_o Asynchronous This signal indicates when one or more LPD-Q devices are active or they are requesting to exit from quiescence.

The following table lists the device interface signals.

Table A-3 LPD-Q device interface signals

Signal Type Clock Description
dev_qreqn_o[NUM_QCHL − 1:0] Output clk This signal indicates when the LPD-Q issues a quiescence entry or exit request to the LPD-Q devices.
dev_qacceptn_i[NUM_QCHL − 1:0] Input Either:
  • Asynchronous, when DEV_Q_CH_SYNC == 1.
  • clk, when DEV_Q_CH_SYNC == 0.
This signal indicates when an LPD-Q device accepts the quiescence request.
dev_qdeny_i[NUM_QCHL − 1:0] This signal indicates when an LPD-Q device denies the quiescence request.
dev_qactive_i[NUM_QCHL − 1:0] Asynchronous This signal indicates when an LPD-Q device is active or it is requesting to exit from quiescence.

The following table lists the Design for Test (DFT) signals.

Table A-4 LPD-Q DFT signals

Signal Type Clock Description
dftcgen Input clk This signal opens the architectural clock gates, and ensures that clk is active during DFT shift mode.
Non-Confidential - BetaPDF file icon PDF version101150_0000_00_en
Copyright © 2018 Arm Limited (or its affiliates). All rights reserved.