A.3 LPC-Q Q-Channel Combiner signals

The following tables show the Low Power Combiner Q-Channel signals.

The following table lists the clock and reset signals.

Table A-9 LPC-Q clock and reset signals

Signal Type Clock Description
clk Input - Clock input.
reset_n Input clk An active-LOW reset input. reset_n can assert asynchronously, but must deassert synchronous to clk.
clk_qactive_o Output clk This signal indicates when the LPC-Q is active and it requires the clk signal.

The following table lists the control interface signals.

Table A-10 LPC-Q control interface signals

Signal Type Clock Description
ctrl_qreqn_i[NUM_CTRL_Q_CHL−1:0] Input Either:
  • Asynchronous, when CTRL_Q_CH_SYNC == 1.
  • clk, when CTRL_Q_CH_SYNC == 0.
This signal indicates when a controller issues a quiescence entry or exit request to the LPC-Q.
ctrl_qacceptn_o[NUM_CTRL_Q_CHL−1:0] Output clk This signal indicates when the LPC-Q accepts the quiescence request.
ctrl_qdeny_o[NUM_CTRL_Q_CHL−1:0] This signal indicates when the LPC-Q denies the quiescence request.
ctrl_qactive_o[NUM_CTRL_Q_CHL−1:0] Asynchronous This signal indicates when one or more LPC-Q devices are active or they are requesting to exit from quiescence.

The following table lists the device interface signals.

Table A-11 LPC-Q device interface signals

Signal Type Clock Description
dev_qreqn_o[NUM_DEV_Q_CHL−1:0] Output clk This signal indicates when the LPC-Q issues a quiescence entry or exit request to the LPC-Q devices.
dev_qacceptn_i[[NUM_DEV_Q_CHL−1:0] Input Either:
  • Asynchronous, when DEV_Q_CH_SYNC == 1.
  • clk, when DEV_Q_CH_SYNC == 0.
This signal indicates when an LPC-Q device accepts the quiescence request.
dev_qdeny_i[NUM_DEV_Q_CHL−1:0] This signal indicates when an LPC-Q device denies the quiescence request.
dev_qactive_i[NUM_DEV_Q_CHL−1:0] Asynchronous This signal indicates when an LPC-Q device is active or it is requesting to exit from quiescence.

The following table lists the Design for Test (DFT) signals.

Table A-12 LPC-Q DFT signals

Signal Type Clock Description
dftcgen Input clk This signal opens the architectural clock gates, and ensures that clk is active during Design for Test (DFT) shift mode.
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