2.2.5 LPD-P configuration parameters

There are multiple configuration parameters that determine the functionality of the Low Power Distributor P-Channel.

The following table shows the LPD-P configuration parameters.

Table 2-2 LPD-P configuration parameters

Parameter Possible settings Default Description
SEQUENCER 0, 1 0

0 = The LPD-P operates as an expander.

1 = The LPD-P operates as a sequencer.

DEV_P_CH_NUM 1-8 -a Sets the number of device (dev_*) P-Channel interfaces in the LPD-P.
P_CH_PACTIVE_LEN 1-32 -a Sets the PACTIVE bus width, for all P-Channels.
P_CH_PSTATE_LEN 1-8 -a Sets the PSTATE bus width, for all P-Channels.
DEV_P_CH_<X>_SAME_EN 0, 1 -a

Controls whether the P-Channel for device <X> performs a transition to a PSTATE value when the device is already in that mode:

0 = The LPD-P does not send a transition on the dev_* P-Channel interface.

1 = The LPD-P sends a transition on the dev_* P-Channel interface.

CTRL_P_CH_SYNC 0, 1 1

0 = A synchronizer is not present on the ctrl_preq_i input.

1 = A synchronizer is present on the ctrl_preq_i input.

DEV_P_CH_SYNC 0, 1 1

0 = Synchronizers are not present on the dev<X>_paccept_i or dev<X>_pdeny_i inputs.

1 = Synchronizers are present on the dev<X>_paccept_i and dev<X>_pdeny_i inputs.

DEV_P_CH_<X>_PWR_PSTATE_MAP_<CTRL_PWR_PSTATE> (<DEV_PWR_PSTATE>)

0b0000-0b1111 when P_CH_PSTATE_LEN ≥ 4.

0b000-0b111 when P_CH_PSTATE_LEN == 3.

0b00-0b11 when P_CH_PSTATE_LEN == 2.

0b0-0b1 when P_CH_PSTATE_LEN == 1.

Sets the device PSTATE[3:0] to the same value as the controller PSTATE[3:0].

Sets the device <x> power mode PSTATE value to use, when the LPD-P receives a given controller power mode PSTATE value:

<CTRL_PWR_PSTATE>
The controller PSTATE[3:0] value, which the LPD-P receives on ctrl_pstate_i[3:0].
<DEV_PWR_PSTATE>
The device PSTATE[3:0] value, which the LPD-P issues on the dev<X>_pstate_o[3:0] output.
DEV_P_CH_<X>_OP_PSTATE_MAP_<CTRL_OP_PSTATE> (<DEV_OP_PSTATE>)

0b0000-0b1111 when P_CH_PSTATE_LEN == 8.

0b000-0b111 when P_CH_PSTATE_LEN == 7.

0b00-0b11 when P_CH_PSTATE_LEN == 6.

0b0-0b1 when P_CH_PSTATE_LEN == 5.

Sets the device PSTATE[7:4] to the same value as the controller PSTATE[7:4].

Sets the device <x> operating mode PSTATE value to use, when the LPD-P receives a given controller operating mode PSTATE value:

<CTRL_OP_PSTATE>
The controller PSTATE[7:4] value, which the LPD-P receives on ctrl_pstate_i[7:4].
<DEV_OP_PSTATE>
The device PSTATE[7:4] value, which the LPD-P issues on the dev<X>_pstate_o[7:4] output.
DEV_P_CH_<X>_PACTIVE_MAP_<N>[P_CH_PACTIVE_LEN] 0 or 1, for each bit -a

This parameter controls how the specified dev<X>_pactive_i[P_CH_PACTIVE_LEN−1:0] bit contributes to the ctrl_pactive_o[P_CH_PACTIVE_LEN−1:0] outputs. There is a parameter for each device P-Channel PACTIVE input. <X> is the device P-Channel number.

<N> is the device PACTIVE bit number, [P_CH_PACTIVE_LEN−1:0], for the specified device P-Channel.

The parameter contains a bit for each controller PACTIVE bit. When a parameter bit is:

0 = The specified dev<X>_pactive_i[P_CH_PACTIVE_LEN−1:0] bit is not OR combined to create the ctrl_pactive_o[P_CH_PACTIVE_LEN−1:0] bit, as specified by the bit position.

1 = The specified dev<X>_pactive_i[P_CH_PACTIVE_LEN−1:0] bit is OR combined to create the ctrl_pactive_o[P_CH_PACTIVE_LEN−1:0] bit, as specified by the bit position.

DEV_P_CH_PREQ_DLY 0, 1 1

Controls whether there is a one clock cycle delay between the assertion of dev<X>_pstate_o and the assertion of dev<X>_preq_o:

0 = Zero clock cycles.

1 = One clock cycle.

a There is no default value for this parameter. The value is set during the render process. See the Arm® CoreLink™ PCK-600 Power Control Kit Configuration and Integration Manual for more information.
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