3.2 Register summary

The Power Policy Unit (PPU) registers occupy a 4KB region.

The following table shows the PPU registers in offset order from the base memory address. See the Arm® Power Policy Unit Architecture Specification, version 1.1 for information about the registers that this document does not describe.

Table 3-1 PPU register summary

Offset Name Type Width Description
0x000 PPU_PWPR RW 32 Power Policy Register.
0x004 PPU_PMER RW 32 Power Mode Emulation Register.
0x008 PPU_PWSR RO 32 Power Status Register.
0x00C - - - Reserved.
0x010 PPU_DISR RO 32 Device Interface Input Current Status Register.
0x014 PPU_MISR RO 32 Miscellaneous Input Current Status Register.
0x018 PPU_STSR RO 32 Stored Status Register.
0x01C PPU_UNLK RW 32 Unlock register.
0x020 PPU_PWCR RW 32 Power Configuration Register.
0x024 PPU_PTCR RW 32 Power Mode Transition Configuration Register.
0x028-0x02C - - - Reserved.
0x030 PPU_IMR RW 32 Interrupt Mask Register.
0x034 PPU_AIMR RW 32 Additional Interrupt Mask Register.
0x038 PPU_ISR RW 32 Interrupt Status Register.
0x03C PPU_AISR RW 32 Additional Interrupt Status Register.
0x040 PPU_IESR RW 32 Input Edge Sensitivity Register.
0x044 PPU_OPSR RW 32 Operating Mode Active Edge Sensitivity Register.
0x048-0x04C - - - Reserved.
0x050 PPU_FUNRR RW 32 Functional Retention RAM Configuration Register.
0x054 PPU_FULRR RW 32 Full Retention RAM Configuration Register
0x058 PPU_MEMRR RW 32 Memory Retention RAM Configuration Register
0x05C-0x15C - - - Reserved.
0x160 PPU_EDTR0 RW 32 Power Mode Entry Delay Register 0.
0x164 PPU_EDTR1 RW 32 Power Mode Entry Delay Register 1.
0x168-0x016C - - - Reserved.
0x170 PPU_DCDR0 RW 32 Device Control Delay Configuration Register 0.
0x174 PPU_DCDR1 RW 32 Device Control Delay Configuration Register 1.
0x178-0xFAC - - - Reserved.
0xFB0 PPU_IDR0 RO 32 PPU Identification Register 0.
0xFB4 PPU_IDR1 RO 32 PPU Identification Register 1.
0xFB8-0xFC4 - - - Reserved.
0xFC8 PPU_IIDR RO 32 3.3 Implementation Identification Register, PPU_IIDR.
0xFCC PPU_AIDR RO 32 Architecture Identification Register.
0xFD0 PID4 RO 32

3.4.1 Peripheral ID 4

0xFD4 PID5 RO 32

3.4.2 Peripheral ID 5

0xFD8 PID6 RO 32

3.4.3 Peripheral ID 6

0xFDC PID7 RO 32

3.4.4 Peripheral ID 7

0xFE0 PID0 RO 32

3.4.5 Peripheral ID 0

0xFE4 PID1 RO 32

3.4.6 Peripheral ID 1

0xFE8 PID2 RO 32

3.4.7 Peripheral ID 2

0xFEC PID3 RO 32

3.4.8 Peripheral ID 3

0xFF0 ID0 RO 32

3.4.9 Component ID 0

0xFF4 ID1 RO 32

3.4.10 Component ID 1

0xFF8 ID2 RO 32

3.4.11 Component ID 2

0xFFC ID3 RO 32

3.4.12 Component ID 3

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