A.4 P2Q Converter signals

The following tables show the P-Channel to Q-Channel Converter signals.

The following table lists the clock and reset signals.

Table A-13 P2Q clock and reset signals

Signal Type Clock Description
clk Input - Clock input.
reset_n Input clk An active-LOW reset input. reset_n can assert asynchronously, but must deassert synchronous to clk.
clk_qactive_o Output clk This signal indicates when the P2Q is active and it requires the clk signal.

The following table lists the control interface signals.

Table A-14 P2Q control interface signals

Signal Type Clock Description
ctrl_preq_i Input Either:
  • Asynchronous, when CTRL_P_CH_SYNC == 1.
  • clk, when CTRL_P_CH_SYNC == 0.
This signal indicates when the controller issues a power mode request to the P2Q.
ctrl_pstate_i[7:0] The power mode and operating mode that is requested when ctrl_preq_i is set HIGH.
ctrl_paccept_o Output clk

This signal indicates when the P2Q accepts the power mode request.

At reset, this signal is LOW.

ctrl_pdeny_o

This signal indicates when the P2Q denies the power mode request.

At reset, this signal is LOW.

ctrl_pactive_o[31:0] Asynchronous This signal indicates the power mode that the device requests. The power mode depends on the value of dev_qactive_i and the configuration of the CTRL_P_CH_PACTIVE_MAP[31:0] parameter.

The following table lists the device interface signals.

Table A-15 P2Q device interface signals

Signal Type Clock Description
dev_qreqn_o Output clk

This signal indicates when the P2Q issues a quiescence entry or exit request to the Q-Channel device.

At reset, this signal is LOW.

dev_qacceptn_i Input Either:
  • Asynchronous, when DEV_Q_CH_SYNC == 1.
  • clk, when DEV_Q_CH_SYNC == 0.
This signal indicates when the Q-Channel device accepts the quiescence request.
dev_qdeny_i This signal indicates when the Q-Channel device denies the quiescence request.
dev_qactive_i Asynchronous This signal indicates when the Q-Channel device is active or it is requesting to exit from quiescence.

The following table lists the Design for Test (DFT) signals.

Table A-16 P2Q DFT signals

Signal Type Clock Description
dftcgen Input clk This signal opens the architectural clock gates, and ensures that clk is active during DFT shift mode.
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