A.2 LPD-P P-Channel Distributor signals

The following tables show the Low Power Distributor P-Channel signals.

The following table lists the clock and reset signals.

Table A-5 LPD-P clock and reset signals

Signal Type Clock Description
clk Input - Clock input.
reset_n Input clk An active-LOW reset input. reset_n can assert asynchronously, but must deassert synchronous to clk.
clk_qactive_o Output clk This signal indicates when the LPD-P is active and it requires the clk signal.

The following table lists the control interface signals.

Table A-6 LPD-P control interface signals

Signal Type Clock Description
ctrl_preq_i Input Either:
  • Asynchronous, when CTRL_P_CH_SYNC == 1.
  • clk, when CTRL_P_CH_SYNC == 0.
This signal indicates when the controller issues a power mode request to the LPD-P.
ctrl_pstate_i[P_CH_PSTATE_LEN−1:0] The power mode and operating mode that is requested when ctrl_preq_i is set HIGH.
ctrl_paccept_o Output clk

This signal indicates when all the LPD-P devices accept the power mode request.

At reset, this signal is LOW.

ctrl_pdeny_o

This signal indicates when one or more LPD-P devices deny the power mode request.

At reset, this signal is LOW.

ctrl_pactive_o[P_CH_PACTIVE_LEN−1:0] Asynchronous This signal indicates the combined power mode that the device dev<X>_pactive_i[P_CH_PACTIVE_LEN−1:0] signals request.

The following table lists the device interface signals.

Table A-7 LPD-P device interface signals, where X is the number of the interface

Signal, where <X> == 1-DEV_P_CH_NUM Type Clock Description
dev<X>_preq_o Output clk

This signal indicates when the LPD-P issues a power mode request to the LPD-P devices.

At reset, this signal is LOW.

dev<X>_pstate_o[P_CH_PSTATE_LEN−1:0] The power mode and operating mode that is sent to device <X> when dev<X>_preq_o is set HIGH.
dev<X>_paccept_i Input Either:
  • Asynchronous, when DEV_P_CH_SYNC == 1.
  • clk, when DEV_P_CH_SYNC == 0.
This signal indicates when an LPD-P device accepts the power mode request.
dev<X>_pdeny_i This signal indicates when an LPD-P device denies the power mode request.
dev<X>_pactive_i[P_CH_PACTIVE_LEN−1:0] Asynchronous This signal indicates the power mode that device <X> requests.

The following table lists the Design for Test (DFT) signals.

Table A-8 LPD-P DFT signals

Signal Type Clock Description
dftcgen Input clk This signal opens the architectural clock gates, and ensures that clk is active during DFT shift mode.
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