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There are multiple configuration parameters that modify the functionality of the Clock Controller.
The following table shows the CLK-CTRL configuration parameters.
Table 2-5 CLK-CTRL configuration parameters
|NUM_Q_CHL||1-8||1||Sets the number of clock device Q-Channel interfaces in the CLK-CTRL.|
|NUM_QACTIVE_ONLY||0-32||1||Sets the number of QACTIVE only Q-Channels.|
0 = A synchronizer is not present on the hc_qreqn_i input.
1 = A synchronizer is present on the hc_qreqn_i input.
0 = A synchronizer is not present on the pwr_qreqn_i input.
1 = A synchronizer is present on the pwr_qreqn_i input.
0 = Synchronizers are not present on the clk_qacceptn_i[N] or clk_qdeny_i[N] inputs.
1 = Synchronizers are present on the clk_qacceptn_i[N] and clk_qdeny_i[N] inputs.
Where [N] = [NUM_Q_CHL−1:0].
0 = Support for denying a quiescence request by using QACTIVE is not included.
1 = Support for denying a quiescence request using QACTIVE is included. Synchronizers are included on the clk_qactive_i[N] inputs, where these signals are used internally.
Note:The path from a device to the controller QACTIVE is combinatorial, irrespective of whether synchronizers are present.