A.5 CLK-CTRL signals

The following tables show the Clock Controller signals.

The following table lists the clock and reset signals.

Table A-17 CLK-CTRL clock and reset signals

Signal Type Clock Description
clk Input - Clock input.
reset_n Input clk An active-LOW reset input. reset_n can assert asynchronously, but must deassert synchronous to clk.

The following table lists the hierarchical clock control signals.

Table A-18 CLK-CTRL hierarchical clock control signals

Signal Type Clock Description
hc_qreqn_i Input Either:
  • Asynchronous, when HC_Q_CH_SYNC == 1.
  • clk, when HC_Q_CH_SYNC == 0.
This signal indicates when the controller issues a quiescence entry or exit request to the CLK-CTRL.
hc_qacceptn_o Output clk This signal indicates when the CLK-CTRL accepts the quiescence request.
hc_qdeny_o This signal indicates when the CLK-CTRL denies the quiescence request.
hc_qactive_o This signal indicates when one or more CLK-CTRL devices are active or they are requesting to exit from quiescence.

The following table lists the hierarchical power control signals.

Table A-19 CLK-CTRL hierarchical power control signals

Signal Type Clock Description
pwr_qreqn_i Input Either:
  • Asynchronous, when PWR_Q_CH_SYNC == 1.
  • clk, when PWR_Q_CH_SYNC == 0.
This signal indicates when the controller issues a quiescence entry or exit request to the CLK-CTRL.
pwr_qacceptn_o Output clk This signal indicates when the CLK-CTRL accepts the quiescence request.
pwr_qdeny_o This signal indicates when the CLK-CTRL denies the quiescence request.
pwr_qactive_o This signal indicates when one or more CLK-CTRL devices are active or they are requesting to exit from quiescence.

The following table lists the clock device interface signals.

Table A-20 CLK-CTRL clock device interface signals

Signal Type Clock Description
clk_qreqn_o[NUM_Q_CHL − 1:0] Output clk This signal indicates when the CLK-CTRL issues a quiescence entry or exit request to the CLK-CTRL devices.
clk_qacceptn_i[NUM_Q_CHL − 1:0] Input Either:
  • Asynchronous, when CLK_Q_CH_SYNC == 1.
  • clk, when CLK_Q_CH_SYNC == 0.
This signal indicates when a CLK-CTRL device accepts the quiescence request.
clk_qdeny_i[NUM_Q_CHL − 1:0] This signal indicates when a CLK-CTRL device denies the quiescence request.
clk_qactive_i[NUM_Q_CHL + NUM_QACTIVE_ONLY − 1:0] Asynchronous This signal indicates when a CLK-CTRL device is active or it is requesting to exit from quiescence.

The following table lists some miscellaneous signals.

Table A-21 CLK-CTRL other signals

Signal Type Clock Description
clken_o Output clk When HIGH, this signal enables the clk signal for downstream devices.
clk_force_i Input Asynchronous When HIGH, it disables the CLK-CTRL clock gating mechanism.
entry_delay_i[7:0] Input Asynchronous Sets the value of the quiescence entry delay. Allows you to add 0-255 clk cycles of hysteresis to the quiescence entry sequence.
dftcgen Input Asynchronous This signal opens the architectural clock gates, and ensures that clk is active during shift mode.
Non-Confidential - BetaPDF file icon PDF version101150_0000_00_en
Copyright © 2018 Arm Limited (or its affiliates). All rights reserved.