Arm CoreLink PCK-600 Power Control Kit Technical Reference Manual : 2.6.1 PPU configuration parameters

2.6.1 PPU configuration parameters

There are multiple configuration parameters that configure or modify the functionality of the Power Policy Unit.

Table 2-6 PPU configuration parameters

Parameter	Permitted values	Usage constraints	Description
DEVCHAN_CFG	0-8	-	Number and type of device interface LPI: 0 = A single P-Channel. 1-8 = A Q-Channel PPU with DEVCHAN_CFG Q-Channel interfaces.
DEV_PREQ_DLY	0-3	Ignored if DEVCHAN_CFG > 0.	Delay between dev_pstate_o and dev_preq_o.
PCSM_PREQ_DLY	0-3	-	Delay between pcsm_pstate_o and pcsm_preq_o.
DEF_PWR_POLICY	`0b0000`, `0b1000`	-	Default value of the PPU_PWPR.PWR_POLICY register field.
DEF_PWR_DYN_EN	0, 1	DEF_PWR_POLICY mode must support dynamic.	Default value of the PPU_PWPR.PWR_DYN_EN register bit.
DEF_OP_POLICY	0-NUM_OPMODE_CFG	Ignored if DEVCHAN_CFG > 0.	Default value of the PPU_PWPR.OP_POLICY register field.
DEF_OP_DYN_EN	0, 1	Ignored if DEVCHAN_CFG > 0 or NUM_OPMODE_CFG == 0.	Default value of the PPU_PWPR.OP_DYN_EN register bit.
ISO_CLKEN_DLY_CFG	0-255	-	Default value of ISO_CLKEN_DLY, in PPU clk cycles.
CLKEN_RST_DLY_CFG	0-255	-	Default value of CLKEN_RST_DLY, in PPU clk cycles.
RST_HWSTAT_DLY_CFG	0-255	-	Default value of RST_HWSTAT_DLY, in PPU clk cycles.
CLKEN_ISO_DLY_CFG	0-255	-	Default value of CLKEN_ISO_DLY, in PPU clk cycles.
ISO_RST_DLY_CFG	0-255	-	Default value of ISO_RST_DLY, in PPU clk cycles.
FUNC_RET_RAM_REG_CFG	0, 1	Static FUNC_RET must be enabled, that is, STA_FUNC_RET_SPT_CFG == 1.	Enable FUNC_RET RAM retention configuration register, PPU_FUNRR.
FULL_RET_RAM_REG_CFG	0, 1	Static FULL_RET must be enabled, that is, STA_FULL_RET_SPT_CFG == 1.	Enable FULL_RET RAM retention configuration register, PPU_FULRR.
MEM_RET_RAM_REG_CFG	0, 1	Static MEM_RET must be enabled, that is, STA_MEM_RET_SPT_CFG == 1.	Enable MEM_RET RAM retention configuration register, PPU_MEMRR.
WARM_RST_DEVREQEN_CFG	0, 1	-	Default value of the PPU_PTCR.WARM_RST_DEVREQEN register bit.
DBG_RECOV_PORST_CFG	0, 1	Ignored if STA_DBG_RECOV_SPT_CFG == 0.	Default value of the PPU_PTCR.DBG_RECOV_PORST_EN register bit.
NUM_OPMODE_CFG	0-15	Ignored if DEVCHAN_CFG > 0.	Number of operating modes.
OP_ACTIVE_CFG	0, 1	Ignored if NUM_OPMODE_CFG == 0, otherwise: When OP_ACTIVE_CFG == 0, then NUM_OPMODE_CFG must be between 1 and 8. When OP_ACTIVE_CFG == 1, then NUM_OPMODE_CFG must be 1, 3, 7, or 15.	Operating mode active configuration. Controls how the PPU responds to PACTIVE[31:16]: 0 = Ladder use model. 1 = Independent use model. See the Arm^® Power Policy Unit Architecture Specification, version 1.1 for more information.
STA_POLICY_OP_IRQ_CFG	0, 1	Must be 0 when NUM_OPMODE_CFG == 0.	Enable static operating policy transition completion.
STA_POLICY_PWR_IRQ_CFG	0, 1	Must be 0 when NUM_OPMODE_CFG == 0.	Enable static power policy transition completion.
LOCK_CFG	0, 1	At least one DYN_x_SPT_CFG == 1.	Enable Lock support.
SW_DEV_DEL_CFG	0, 1	-	Enables software to write to the PPU_DCDR0 register and alter the device control delay parameters.
PWR_MODE_ENTRY_DEL_CFG	0, 1	-	Enables software to write to the PPU_EDTR0 register and alter the power mode entry delay parameters.
STA_OFF_EMU_SPT_CFG	0, 1	-	Enable static OFF_EMU.
STA_MEM_RET_SPT_CFG	0, 1	-	Enable static MEM_RET.
STA_MEM_RET_EMU_SPT_CFG	0, 1	STA_MEM_RET_SPT_CFG == 1.	Enable static MEM_RET_EMU.
STA_LGC_RET_SPT_CFG	0, 1	DEVCHAN_CFG == 0 && STA_MEM_OFF_SPT_CFG == 1.	Enable static LOGIC_RET.
STA_FULL_RET_SPT_CFG	0, 1	-	Enable static FULL_RET.
STA_MEM_OFF_SPT_CFG	0, 1	-	Enable static MEM_OFF.
STA_FUNC_RET_SPT_CFG	0, 1	-	Enable static FUNC_RET.
STA_DBG_RECOV_SPT_CFG	0, 1	Ignored if DEVCHAN_CFG > 0.	Enable static DBG_RECOV.
DYN_OFF_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1.	Enable dynamic OFF.
DYN_OFF_EMU_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && STA_OFF_EMU_SPT_CFG == 1 && DYN_OFF_SPT_CFG == 1.	Enable dynamic OFF_EMU.
DYN_MEM_RET_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && STA_MEM_RET_SPT_CFG == 1.	Enable dynamic MEM_RET.
DYN_MEM_RET_EMU_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && STA_MEM_RET_EMU_SPT_CFG == 1 && DYN_MEM_RET_SPT_CFG == 1 && STA_MEM_RET_SPT_CFG == 1.	Enable dynamic MEM_RET_EMU.
DYN_LGC_RET_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && STA_LGC_RET_SPT_CFG == 1 && DYN_MEM_OFF_SPT_CFG == 1 && STA_MEM_OFF_SPT_CFG == 1 && DEVCHAN_CFG == 0.	Enable dynamic LOGIC_RET.
DYN_FULL_RET_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && STA_FULL_RET_SPT_CFG == 1.	Enable dynamic FULL_RET.
DYN_MEM_OFF_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && STA_MEM_OFF_SPT_CFG == 1.	Enable dynamic MEM_OFF.
DYN_FUNC_RET_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && STA_FUNC_RET_SPT_CFG == 1.	Enable dynamic FUNC_RET.
DYN_ON_SPT_CFG	0, 1	-	Enable dynamic ON.
DYN_WRM_RST_SPT_CFG	0, 1	DYN_ON_SPT_CFG == 1 && DEVCHAN_CFG == 0.	Enable dynamic WARM_RST.
DEV_SYNC_EN	0, 1	-	If set to 1, adds synchronizers to either: dev_paccept_i and dev_pdeny_i when DEVCHAN_CFG == 0. dev_qacceptn_i[DEVCHAN_CFG − 1:0] and dev_qdeny_i[DEVCHAN_CFG − 1:0] when DEVCHAN_CFG > 0.
DEV_ACTIVE_SYNC_EN	0, 1	-	If set to 1, adds synchronizers to either: dev_pactive_i when DEVCHAN_CFG == 0. dev_qactive_i[DEVCHAN_CFG − 1:0] when DEVCHAN_CFG > 0.
PCSM_SYNC_EN	0, 1	-	Add synchronizer on pcsm_paccept_i.
QCLK_SYNC_EN	0, 1	-	Add synchronizer on ppuclk_qreqn_i.
OFF_MEM_RET_TRANS_CFG	0, 1	STA_MEM_RET_SPT_CFG == 1.	Enable direct transitions between OFF and MEM_RET.
PCSM_OFF_INIT	0, 1	-	Enables a PCSM initialization handshake when the default policy is OFF.
OPMODE_PCSM_SPT_CFG	0, 1	Ignored if NUM_OPMODE_CFG == 0.	Enables OPMODE bits on the PCSM and PCSM handshakes on OPMODE only transitions.
UARCH	0-2	Value of 2 is only allowed if PWR_MODE_ENTRY_DEL_CFG == 1 \|\| NUM_OPMODE_CFG > 0.	Defines the microarchitecture of the design: 0 = Minimum area. 1 = Balance. 2 = Performance.

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