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The Low Power Distributor P-Channel (LPD-P) component enables a P-Channel controller to control, and potentially sequence, multiple P-Channel devices.
The LPD-P supports from 1-8 device P-Channel interfaces and can be configured to operate in the following modes:
The following figure shows the main interfaces on the LPD-P.
The control P-Channel (ctrl_* signals) receives power mode requests from the P-Channel controller. The LPD-P uses the device P-Channels (dev<X>_* signals) to send the power mode requests to the devices. The LPD-P uses clk_qactive_o to indicate when it requires a clock signal, clk.
The control P-Channel supports the all the PPU power modes and 16 operating modes. The ctrl_pactive_o[P_CH_PACTIVE_LEN−1:0] outputs are the logical OR of the multiple device inputs, dev<X>_pactive_i[P_CH_PACTIVE_LEN−1:0]. The path from the dev<X>_pactive_i signals to the ctrl_pactive_o output is a combinatorial path.
During implementation, you can configure which dev<X>_pactive_i inputs are included in the OR function. See 2.2.4 PACTIVE remapping for more information.
The clk_qactive_o is a Q-Channel signal that is HIGH:
The type of response that the LPD-P generates to the controller depends on the responses that the LPD-P receives from the devices:
The LPD-P denies a controller request, when any device denies the request by setting dev<X>_pdeny_i HIGH. The ctrl_pdeny_o signal remains HIGH until all devices that accepted the request, revert to their previous PSTATE value.
System implementations of the LPD-P in non-PCSA compliant architectures are limited to a maximum PSTATE length of 4 bits (16 power modes). The PSTATE[7:4] bits are reserved for PCSA operating modes.
The LPD-P supports optional resynchronization on either or both the controller and device interfaces. The LPD-P can also be configured to set the device PSTATE value, one clock cycle before the LPD-P asserts dev<X>_preq_o.