3.4 Implementation-defined identification registers

The PPU has some ID registers that are at the end of the 4KB memory region. Software can use these registers to discover which components are present in an SoC.

3.4.1 Peripheral ID 4

Peripheral ID 4 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-2 Peripheral ID 4 Register bit assignments
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The following table shows the bit assignments.

Table 3-3 Peripheral ID 4 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:4] 4KB_COUNT 0x0 Indicates that the PPU registers occupy a single 4KB page.
[3:0] JEP106_CONT_CODE 0x4 Indicates how many Continuation Codes (0x7F) an Arm device requires. For identifying an Arm device or product, the Standard Manufacturer’s Identification Code specifies a requirement of four Condition Codes.

3.4.2 Peripheral ID 5

Peripheral ID 5 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-3 Peripheral ID 5 Register bit assignments
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The following table shows the bit assignments.

Table 3-4 Peripheral ID 5 Register bit assignments

Bits Name Default Function
[31:0] - 0x0 Reserved.

3.4.3 Peripheral ID 6

Peripheral ID 6 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-4 Peripheral ID 6 Register bit assignments
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The following table shows the bit assignments.

Table 3-5 Peripheral ID 6 Register bit assignments

Bits Name Default Function
[31:0] - 0x0 Reserved.

3.4.4 Peripheral ID 7

Peripheral ID 7 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-5 Peripheral ID 7 Register bit assignments
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The following table shows the bit assignments.

Table 3-6 Peripheral ID 7 Register bit assignments

Bits Name Default Function
[31:0] - 0x0 Reserved.

3.4.5 Peripheral ID 0

Peripheral ID 0 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-6 Peripheral ID 0 Register bit assignments
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The following table shows the bit assignments.

Table 3-7 Peripheral ID 0 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:0] PART_NUMBER[7:0] 0xB6 Part number for the PCK-600 PPU.

3.4.6 Peripheral ID 1

Peripheral ID 1 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-7 Peripheral ID 1 Register bit assignments
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The following table shows the bit assignments.

Table 3-8 Peripheral ID 1 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:4] JEP_ID[3:0] 0xB JEP106 ID code[3:0].
[3:0] PART_NUMBER[11:8] 0x0 Part number.

3.4.7 Peripheral ID 2

Peripheral ID 2 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-8 Peripheral ID 2 Register bit assignments
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The following table shows the bit assignments.

Table 3-9 Peripheral ID 2 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:4] REV 0x0 Major revision.
[3] JDEC 0x1 Indicates the use of a JEDEC‑assigned value.
[2:0] JEP106_ID[6:4] 0x3 JEP106 ID code[6:4].

3.4.8 Peripheral ID 3

Peripheral ID 3 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-9 Peripheral ID 3 Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-10 Peripheral ID 3 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:4] REVAND 0x0 Minor revision.
[3:0] CUSTOMER_MOD 0x0 Customer modification.

3.4.9 Component ID 0

Component ID 0 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-10 Component ID 0 Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-11 Component ID 0 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:0] PRMBL_0 0x0D Preamble 0.

3.4.10 Component ID 1

Component ID 1 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-11 Component ID 1 Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-12 Component ID 1 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:4] CLASS 0xF Indicates the component class that this component belongs to.
[3:0] PRMBL_1 0x0 Preamble 1.

3.4.11 Component ID 2

Component ID 2 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-12 Component ID 2 Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-13 Component ID 2 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:0] PRMBL_2 0x05 Preamble 2.

3.4.12 Component ID 3

Component ID 3 Register.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 3.2 Register summary.

The following figure shows the bit assignments.

Figure 3-13 Component ID 3 Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-14 Component ID 3 Register bit assignments

Bits Name Default Function
[31:8] - 0x0 Reserved.
[7:0] PRMBL_3 0xB1 Preamble 3.
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